Taking System Design to a Higher Level
To the mantra of "Faster—Cheaper—Smaller" designers are adding another term, "Higher." System-level designers, pushed by the expanding role of system-on-a-chip (SoC) technology, are looking for ways to accelerate system design time while lowering design costs.
Many system houses have come to the realization that to accomplish these two goals, they need to reinvent the way systems are designed. Raising the level at which critical system architectural and performance decisions are made is critical to continuing the successful completion of ever-more-complex electronic systems. Keys to raising the design level are the availability of different design methodologies coupled with design tools that can navigate designs at abstraction levels above RTL.
Driving Forces for Higher-Level Design
System designers know that sooner is better. The earlier in the design process you can locate a problem, the less time and resources it costs to fix the problem. Every time a design is synthesized from one level to a more detailed level, such as behavioral to RTL or RTL to gate, it takes longer to do a design simulation. Furthermore, problems that occur at higher levels of design abstraction are often hidden by the details of a lower-level abstraction, making design debugging more difficult and time consuming. Lost time and added expense are pushing design, analysis, and verification above the RT.
Above and Beyond HDLs
While Verilog and VHDL are reasonable design languages for RTL designs, neither HDL is adequate for behavioral level system design. In addition, many systems require design knowledge of both languages. For example, a Verilog-based system may use VHDL models for legacy silicon IP. EDA-tool and system-design companies are investigating a number of alternative languages for high-level design, including enhanced versions of Verilog and VHDL along with other design languages.
Among Verilog and VHDL alternatives are supersets of C/C++, Java, and proprietary design languages. At this time, the C/C++ variants seem to have the edge, since the languages are already well known by system designers for both hardware modeling and software design.
Proprietary languages, which arguably may be better optimized for system-level hardware design, suffer from limited portability and lack of widespread acceptance by the design community. Design interoperability, the seamless flow of design data from one tool to another, is a big problem with existing VHDL- and Verilog-based systems. Using behavioral level design languages, especially proprietary languages, will only accentuate tool-to-tool interface problems.
Any choice of a "new" high-level system-design language will require language standardization before it becomes a common design vehicle. Standardization, such as that needed by VHDL and Verilog, is usually measured in years - the analog/mixed-signal (A/MS) extensions for Verilog and VHDL took about 10 years apiece before they became IEEE-endorsed standards in 1999.
Additional Future System-Level Design Needs
Hardware/software (HW/SW) co-design tools have become a common part of many system-level designs. However, today's tools are both inadequate for evolving SoC designs comprising tens-of-millions of logic gates and are difficult to use. When new system-design languages evolve to the point where they are widely used, HW/SW co-design tools will also have to have developed to the point where they are easier to learn and apply and have the capacity to handle system complexities measured in many millions of gates.
A major hole in co-design tools, which have concentrated on HW/SW co-simulation, is a system-partitioning capability. A key design consideration for any electronic system is how to partition required system functions between hardware and software based on performance, cost, size, and other system-design constraints. At this time, there are no automatic tools for constraint-based partitioning. The partitioning function is manual, based on a designer's expertise and the results of behavioral level virtual-prototype simulation. The emergence of a tool to automate this function would be invaluable in shortening time-to-market for future system designs.
The Wish List
Taking the development and acceptance of one or more new high-level design languages as a "given," we will need new tools and standards for tool interoperability in place to be able to meet future system-design requirements. The needed tools will have to handle HW/SW co-design at a behavioral level, including partitioning, for systems at hundred-million-gate complexities and beyond. Finally, designers will have to develop new design methodologies, concentrating on higher-level design and analysis to take advantage of the new design tools and languages.
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