Benchmarking an ARM-based SoC using Dhrystone: A VFT perspective

Neha Srivastava, and Aashish Mittal, Freescale Semiconductor

November 4, 2012

Neha Srivastava, and Aashish Mittal, Freescale Semiconductor

Results of the SoC performance benchmarks
In the example described here, the performance of the Cortex-M4 operating in copyback mode was considerably better then when in write-through mode. Below is a VCD snapshot to illustrate the ports used as measurement points (start and stop for the last n loops used for measuring execution time) and the pads showing the status of the run (running/execution complete/pass/fail).



Click on image to enlarge.
The overall results obtained from the tester provided close correlation with the performance predicted by the core platform design team based on their RTL simulations as well as those provided by the application teams running in a more robust software environment. These correlations gave us confidence that the VFT setup would provide credible results.

The configurations presented here for Dhrystone performance measurement represent only a partial subset of the possible options. The intent is to show relative performance ranges and not a definitive set of absolute Dhrystone performance metrics. The table below summarizes the performance metrices of the ARM SoC design.


As shown above, the differences in the measured cache-enabled performance are mostly due to the variations in the processor instruction set architectures and microarchitecture implementations. The numbers for copy-back mode are significantly improved over the numbers with write-through. This is because the write-through for each instruction consumes more execution time than a copy-back from cache at the end of loops for the significant locations.

For the specific design example considered, the Cortex-A5 caches only do copy-back, whereas write-through vs. copy-back option is applicable only for CM4, as also reflected in the results.

Conclusions
Performance measurements taken from a bare-metal execution of the Dhrystone 2.1 benchmark on a dual-core SoC proved to be straightforward once we understood the specifics of the runtime environment and were able to instrument the code to provide the appropriate event signalling.

The Dhrystone performance benchmark is a fairly simple one to use but only if the user is clear about how to plug it in and run it on their individual setups. This is particularly true if it involves minor modifications for system compatibility or uses a different way of gathering the result numbers from their setup (for example, in our case, getting the numbers directly from tester).

For designers unfamiliar with the Dhrystone reference documentation, it is easy to get lost in the small print and excessive details. While useful for in-depth architectural analysis, much of what is available is not useful in helping the designer understand what is needed for the actual execution and result calculation.

For the sake of simplicity, we’ve focused on crucial, to-the-point steps, separating them from the good-to-have (but not necessarily relevant) ones. With minor tweaks, the procedures described here can be used by developers across the execution flow and are adaptable for use on any tester (or any benchmarking setup, for that matter).

Neha Srivastava is a lead engineer at Freescale Semiconductors (Noida, India Design Centre), working in the Automotive and Industrial Solution Group (AISG) for over 5 years now. She has a Bachelor of Engineering (B.E.) degree from Birla Institute of Technology. She has worked on multiple SoCs in front-end verification and Verification for Testing domain with the areas of interest being low power designs, safety architectures and high performance systems. She can be reached at Neha.Srivastava@freescale.com.

Aashish Mittal is a principal design engineer at Freescale Semiconductors (Noida, India Design Centre), working in the Automotive and Industrial Solution Group(AISG) for over 12 years. He has a Master of Technology from Banaras Hindu University He has worked on multiple SoCs in front-end verification, Testbench Integration and Verification for Testing domain with the areas of interest being dual core, security , debug and low power architecture. He can be reached at aashish@freescale.com.

References
1. ARM apps note on Dhrystone benchmarking for ARM Cortex Processors.
2. ARM apps note on benchmarking with ARMulator.
3. White-paper on Dhrystone Benchmark by ECL.
4. Wikipedia Reference for Dhrystone.