Reinventing JTAG for SoC debugging
IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades. Although the new IEEE 1149.7 has not been finalized, its direction and its benefits to engineers--particularly those developing and debugging software for complex systems--are well defined.
IEEE 1149.7 was created with several goals in mind--to maintain backward compatibility with 1149.1 and improve debug performances. IEEE 1149.7 also reduces System-on-Chip (SoC) pin-count requirements and provides standardized power-saving operating conditions. While IEEE 1149.7 adds substantial functionality to the existing standard, it's important to note that IEEE 1149.7 isn't a replacement for IEEE 1149.1. Backward compatibility is maintained so that any board or system that integrates chips that support either standard is amenable to test or debug procedures.
The new standard offers designers several benefits, including:
• The ability to control debug-logic power consumption in an industry standard way. Whereas IEEE 1149.1 had a single "always on" state, IEEE 1149.7 offers four selectable power modes to enable ultra-low-power devices.
• The ability to quickly access a specific device in a system with multiple devices. By implementing a system level bypass, the scan chain is drastically shorter, which directly improves the debugging experience.
• The introduction of a star topology to complement the standard serial topology. Designers working with stacked-die devices, multi-chip modules and plug-in cards will favor the star topology because it simplifies the physical interdevice connections.
• Two-pin operation in addition to the four-pin operation required in IEEE 1149.1. Since most of today's systems integrate multiple ICs and have severe size constraints, reducing the number of pins and traces will help designers meet their form factor goals and allowing for additional functional pins and/or low package cost. Background Data transfers (BDX) provide an industry-standard method for sending instrumentation data. Instrumentation information was previously implemented in vendor-specific methods, making tools support difficult. Standardization will provide users with a greater selection of products.
Since much of the terminology and techniques used in the new standard are inherited from a present one, a brief review of IEEE 1149.1 will be useful.
In the mid-1980s, multilayer circuit boards and non-lead-frame ICs were becoming standard. But because the connections between ICs were not available to test probes in these subsystems, testing was becoming more and more difficult. The Joint Test Action Group (JTAG) was formed in 1985 to solve this problem.
Although considered synonymous with JTAG, the IEEE 1149.1 standard's official title is the Standard Test Access Port and Boundary-Scan Architecture. Among other things, it defines test access ports (TAPs) used for testing PC boards using boundary scan.
Today, JTAG is used not only for PC board testing but also to access sub-blocks of integrated circuits and to debug embedded systems.
The JTAG ecosystem begins with IC designers embedding test logic in each chip and connecting internal registers in the chip to JTAG scan chains. The hardware components of IEEE 1149.1 consist of:
• TAPs. Four mandatory pins are: TDI (test data in), TDO (test data out), TMS (test mode select), and TCK (test clock). An optional TRST/reset pin is also defined. When driven low, it resets the internal state machine.
• TAP controller: A finite state machine with 16 states with TMS and TCK as its inputs. Outputs include ClockDR, UpdateDR, shiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK, and the optional TRST.
• Instruction register.
• Test data register.
Figure 1 shows the basic IC architecture of IEEE 1149.1.
Test engineers use these structures as the access points for built-in self-test (BIST). Together, JTAG and BIST are widely used to deploy low overhead embedded test solutions that detect static faults such as shorts, opens, and logic errors.
For software debugging, design engineers use an in-circuit emulator to access an on-chip debug module, which is integrated into the CPU over the JTAG interface. This debug module provides software developers the ability to load, run, halt, and step the CPU.