An introduction to Synchronized Ethernet

Slobodan Milijevic

March 3, 2009

Slobodan Milijevic

Synchronized Ethernet requirements
From the discussion so far, it appears that the only requirement for a PLL used in SyncE is to clean jitter from the recovered clock, which can be accomplished with general purpose PLLs. However, the PLL used in SyncE must provide additional functions beyond jitter cleaning.

For example, if the receiving PHY device (Node 2, PHY 1 in Figure 3) gets disconnected from the line, the recovered clock frequency will either stop or start to drift depending on the implementation of the clock recovery circuit. The general purpose PLL will pass this big frequency change to the transmitting PHY device (Node 2, PHY 2 in Figure 3). As a result, not only is the transmission of synchronization signal going to fail, but the data transmission could fail as well.

The PLL used in SyncE must be able to detect failure of the recovered clock and switch the PLL to either another good reference in the system or into holdover mode. Requirements for SyncE are outlined in the timing characteristics of synchronous Ethernet equipment clock (ITU G.8262/Y1362) specifications. These specifications are based on ITU-T G.813 specification for SDH clocks. The major requirements of ITU-T G.8262/Y1362 are:

• Free-run accuracy: The accuracy of PLL output when it is not driven by a reference should be equal or better than +/-4.6 ppm (part per million) over a time period of one year. This is a very accurate clock relative to the clock accuracy for traditional Ethernet (+/-100 ppm).
• Holdover: The PLL constantly calculates the average frequency of the locked reference. If the reference fails and no other references are available, the PLL goes into holdover mode and generates an output clock based on a calculated average value. Holdover stability depends on the resolution of the PLL averaging algorithm and the frequency stability of the oscillator used as the PLL master clock.
• Reference monitoring: The PLL needs to constantly monitor the quality of its input references. If the reference deteriorates (disappears or drifts in frequency), then the PLL raises an alarm (interrupt) and switches to another valid reference.
• Hitless reference switching: If the PLL's reference fails, then it will lock to another available reference without phase disturbances at its output.
• Jitter and wander filtering: The PLL can be viewed as a jitter and wander filter. The narrower the loop bandwidth, the better the jitter and wander attenuation.
• Jitter and wander tolerance: The PLL should tolerate large jitter and wander at its input and still maintain synchronization without raising any alarms.

These stringent requirements can be met only with a digital PLL (DPLL) similar to DPLLs used for SONET/SDH clocks. The major difference is that a SyncE DPLL needs to be able to lock and generate clock frequencies used in Ethernet (25MHz, 125MHz and 156.25MH) as opposed to telecom clocks (19.44MHz, 155.52MHz) used in SONET/SDH.