An introduction to Synchronized Ethernet
Implementation of SyncE systems
Carrier-grade SyncE systems must provide highly reliable operation under all network conditions. To do this, the most critical components within the system are made redundant, including timing.
Timing in a carrier-grade SyncE system is comprised of two timing cards that feed clocks to multiple line cards via a common backplane, as shown in Figure 4. All line cards synchronize to the clock coming from an active timing card. If the active timing card clock fails (for example, the card is unplugged), line cards will synchronize to the clock coming from the redundant timing card. Switching from one timing card to the other should not cause any interruption or failure in the system.
Figure 4: Redundant timing in carrier-grade SyncE
Having two timing cards protects against an internal failure if one of the cards fails. As seen in Figure 4, to protect from external clock reference failures, the timing cards are designed to be able to synchronize to more than one reference. A timing card accepts references from multiple sources, selects one, cleans it from phase noise with a DPLL, and distributes it to the line cards via the backplane. The DPLL is the most important part of the timing card. Timing card DPLL references can come externally from a SSU/BITS, internally from line cards, or from the other timing card in the system. Timing card DPLLs should meet all ITU-T G.8262/Y1362 requirements.
As seen in Figure 4, the line cards each have a DPLL that is used for jitter reduction and frequency translation. For example,frequency translation is required to convert from the 25MHz backplane clock to one or more clocks required by the Ethernet PHY, such as 125MHz, 156.25MHz, 155.52MHz or any other.
The line card DPLL must also provide hitless switching between the active and redundant clocks and provide clock continuity for a short period, such as when the active clock unexpectedly disappears before the system detects active reference failure and switches the line card DPLL to lock to the redundant reference. Like any DPLL, a line card DPLL requires a crystal oscillator.
However, this can be a low-cost oscillator as the line card DPLL is not required to go into holdover (except for short time periods when switching between active and redundant clocks). For long-term holdover, the system relies on a timing card DPLL. Therefore, a timing card DPLL requires higher quality crystal oscillators (TCXO, OCXO).
Smaller SyncE systems that do not need timing redundancy will generally have only one DPLL. This DPLL should meet all requirement of the timing card DPLL and the line card DPLL combined. This DPLL should have narrow loop bandwidth, good holdover (TCXO or OCXO required), hitless reference switching and very low intrinsic jitter. Depending on the application, this DPLL might also need to generate telecom frequencies such as 8KHz, 2.048MHz, 1.544MHz, 34.368MHz, 44.736MHz and many others.
Figure 5 illustrates a next-generation Digital Loop Carrier (DLC) requiring Ethernet and telecom clock frequencies. DLCs are installed in the neighborhood to aggregate traffic from multiple POTS, xDSL and T1/E1 to minimize the number of the lines going to the Central Office (CO) and increase xDSL data rates by shortening the length of the copper lines.
Figure 5. Next-generation digital loop carrier
Aggregated traffic is carried to the CO via a fiber cable or several copper lines. Traditionally, DLCs have used SONET/SDH or T3/E3 to transmit data between the DLC and CO. However, these links are being replaced by Ethernet because of its lower capital and operational costs.
Slobodan Milijevic is a senior applications engineer with Zarlink Semiconductor. He can be reached at slobodan.milijevic@zarlink.com.
References
Definitions and terminology for synchronization networks ITU-T Recommendation G.810, 1996
Timing characteristics of SDH equipment slave clocks (SEC) ITU-T Recommendation G.813, 1998
Timing characteristics of synchronous Ethernet equipment slave clock (EEC) ITU-T Recommendation G.8262/Y.1362, 2007
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