Design Con 2015

An introduction to Synchronized Ethernet

Slobodan Milijevic

March 03, 2009

Slobodan MilijevicMarch 03, 2009

Over the past two decades Ethernet has become the dominant technology for data transmission, in particular with telecom and wireless providers, due to its simplicity and low cost. However, the asynchronous nature of Ethernet provides certain transmission challenges.

For example, Time Division Multiplexing (TDM) services such as T1/E1 and SONET/SDH require synchronized clocks at both the source and destination nodes. Similarly, wireless base stations require synchronization to a common clock to ensure a smooth call hand-off between adjacent cells.

While there are several ways to achieve synchronization over Ethernet, one gaining momentum is Synchronous Ethernet (SyncE). SyncE uses the physical layer interface to pass timing from node to node in the same way timing is passed in SONET/SDH or T1/E1. This gives telecom and wireless providers confidence that networks based on SyncE will be not only cost-effective, but also as highly reliable as SONET/SDH and T1/E1 based networks.

As interest from carriers and service providers grows, many Ethernet equipment vendors are developing SyncE enabled equipment targeting this lucrative new market. However, Ethernet equipment designers often lack in-depth understanding of synchronization, and may underestimate the complexity of the issue.

A common assumption is synchronization over Ethernet can be achieved merely by replacing the free-running crystal oscillator used for Ethernet Physical Layer Device (PHY) with a general purpose synchronization device (Phase Locked Loop--PLL).

Certainly, this is not the case and designs based on such an assumption are destined to fail. This article will discuss the basics of Synchronous Ethernet performance, review synchronization concepts and requirements, and highlight some common design hurdles faced by board designers to help ensure right-first-time SyncE designs.

Synchronization in telecom systems
Timing is critical for telecom system performance. Telecom systems are based on time division multiplexing (TDM) technologies (T1/E1 and SONET/SDH), which are best suited for transmission of constant bit rate traffic such as digitized voice and video. TDM technologies support small transmission delay and small transmission delay variation--two key parameters for voice quality and video transmission.

Small transmission delay can only be achieved if data buffering at each node is minimal. This implies that all nodes in a TDM-based network must be tightly synchronized to a common clock in order to prevent data loss. If one node has a slightly different frequency, even for a short period, the buffer at that node will either overflow or underflow and the data sample(s) will be lost or repeated to keep the bit rate constant.

Network synchronization in telecom systems is based on clock hierarchy, with the highest accuracy clock at the top, as illustrated in Figure 1 .

Figure 1: SDH/SONET network synchronization hierarchy

View the full-size image

At the top of the hierarchy is the Primary Reference Clock (PRC) or Primary Reference Source (PRS) with clock accuracy of 10-11. This means that a clock with this accuracy will have one extra or one less pulse for every 1011 pulse relative to the ideal clock. A wristwatch timed with such a clock would be off one second every 1011 seconds (3,172 years).

PRC/PRS can be generated from a cesium (atomic) clock or from cesium clock-controlled radio signals, such as Global Positioning System (GPS), Global Orbiting Navigation Satellite System (GLONASS) and Long Range Navigation System Version C (LORAN-C).

At the next level of hierarchy is Synchronization Supply Unit (SSU) or Building Integrated Timing Supply (BITS). SSU/BITS includes holdover, a feature that allows it to generate a clock with higher accuracy than its intrinsic free-running accuracy for a short period after it loses synchronization with PRC/PRS. SSU/BITS is usually implemented with a Digital Phase Locked Loop (DPLL) driven by a rubidium clock.

The third level is the SDH Equipment Clock (SEC) or SONET Minimum Clock (SMC). SEC/SMC also features holdover, but its holdover and free-run accuracy performance is lower than what is required for SSU/BITS. SEC/SMC is usually implemented with a DPLL driven by an ovenized crystal oscillator (OCXO) or temperature-controlled crystal oscillator (TCXO). It should be noted that the second and lower levels of hierarchy will have clock accuracy equal to PRC/PRS, so long as their path to the PRC/PRS is not broken.

For reliability reasons, it is unrealistic to expect all global telecommunication networks to be synchronized to a single PRC/PRS. Real networks use a flatter timing distribution structure with a number of PRC/PRS running independently. Each telecom provider usually has its own PRC/PRS, which means that the worldwide telecommunication network consists of synchronized islands connected with plesiochronous links.

While PRC/PRS and SSU/BITS are usually implemented as stand-alone products with timing-only functionality (no data transmission), SEC/SMC are almost exclusively implemented as a part of networking product, such as an add-drop multiplexer.

< Previous
Page 1 of 4
Next >

Loading comments...

Parts Search Datasheets.com

KNOWLEDGE CENTER