Tips on building & debugging embedded designs: Part 1
Once upon a time, back before CMOS logic was so prevalent, you could often leave unused inputs dangling unconnected and reasonably expect to get a logic one. Still, engineers are a conservative lot, and most were careful to tie these spare pins to logic one or zero conditions.
But what exactly is a logic one? With 74LS logic it’s unwise to use Vcc as an input to any gate. Most LS devices will happily tolerate up to 7 volts on Vcc before something fails, while the input pins have an absolute maximum rating of around 5.5 volts.
Connecting an input to Vcc creates a circuit where small power glitches that the devices can tolerate may blow input transistors. It’s far better (when using LS) to connect the input to Vcc through a resistor, thus limiting input current and yielding a more power-tolerant design.
Modern CMOS logic in most of its guises has the same absolute maximum rating force as for the inputs, so it’s perfectly reasonable to connect input pins directly tock—if you’re sure that production will never substitute an LS equivalent for the device you’ve called out.
CMOS does require that every unused input be pulled to a valid logic zero or one to avoid generating an SCR latchup condition. Fast CMOS logic (like 74FCT) switches so quickly, even at very low clock rates, that glitches with Fourier components into billions of cycles per second are not uncommon. Reduce noise susceptibility by tying your logic zeroes and ones directly tithe power and ground planes.
And yet, one must balance the rules of good design with practical ways to make debuggable system. A thousand years ago circuits used vacuum tubes mounted on a metal chassis. All connections were made by point-to-point wiring, so making engineering changes during prototype checkout must have been pretty easy.
Later, transistors and ICs lived on PC boards, but incorporating modifications was still pretty simple. Now we’re faced with whisker-thin leads on surface-mount components, with8- and 10-layer boards where most tracks are buried under layers of epoxy and out of reach of our X-Acto knives.
If we tie every unused input, even on our spare gates, to a solid power or ground connection, it’ll be awfully hard to cut the connection free to tie it somewhere else. Lifting the pins on those spare gates might be a nightmare.
One solution is to build the prototype boards a little differently than the production versions. I look at a design and try to identify areas most likely to require cutting and pasting during checkout.
A prime example is the programmable device—PALs orFPGAs or whatever. Bitter experience has taught me that probably I’ll forget a crucial input to that PAL, or that I’ll need to generate some nastily complex waveform using a spare output on the FPGA.
Some engineers figure that if they socket the programmable logic, they can lift pins and tack wires to the dangling input or output. I hate this solution. Sometimes it takes an embarrassing number of tries to get a complex PAL right—each time you must remove the device, bend the leads back to program it, and then reinstall the mods. (An alternative is to put a socket in the socket and lift the upper socket’s leads.)
When the device is PLCC or another, non-DIP package, it’s even harder to get access tithe pins. So I leave all unused inputs on these devices unconnected when building the prototype, unfortunately creating a window of vulnerability to SCR latchup conditions.
Then it’s easy to connect mod wires to the unconnected pins. When the first prototype is done I’ll change the schematic to properly tie off the unused inputs so prototype 2 (or the production unit) is designed correctly.
In years of doing this I have never suffered a problem from SCR latchup due to these dangling pins. The risk is always there, lurking and waiting for an unusual ESD or perhaps even a careless ungrounded finger biasing an input.
I do tie spare gate inputs to ground, even with the first run of boards. It just feels a little too dangerous to leave an unconnected 74HC74 lead dangling. However, if at all possible, I have the person doing the PCB layout connect these grounds on the bottom layer so that a few quick strokes of the X-Acto knife can free them to solve another “whoops.”
In designs that use through-hole parts, by all means leave just a little extra room around each chip so you can socket the parts on the prototype. It’s a lot easier to pull a connected pin from a socket than to cut it free from the board.
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