Evaluating PCB layout tools: A board developer’s perspective
Mentor Graphics PADs:
The PADs platform, even though not as dated as Allegro, has been available for some time now. It is best suited for small to medium complexity boards. Hence, by 2005, PADs had become one of the most widely used platforms for PCB layout. It has its own schematic tools in DxDesigner and PADs logic, but can also work with OrCad capture with some limitations. PADs Logic and DxDesigner are fairly integrated into the tool and easy to work with.
PADs is known for its intuitive and easier to understand GUI. Figure 3 below shows the PADs design rules window showing constraints setup of a particular net class. Notice how the options are comprehensible and straight forward. Even though it is still a hassle to learn PADs, once you get the hang of it, performing tasks is fairly quick and easy. Its hot keys enable the designer to perform tasks quite promptly.
Figure 3: Design Rules window with physical constraints setup based on a particular net class (To view larger image, click here)..
Library creation is much easier with PADs compared to Allegro. Part libraries are fairly easy to manage and maintain. One can find free part libraries online that are already built and time tested and vetted. The file structure is fairly straight forward. Project outputs are uncomplicated to set up.
HyperLynx from Mentor is also another resourceful tool that enables engineers to quickly and accurately analyze signal integrity at all stages of design life cycles and follows its intuitive GUI from PADs. Hyperlynx thermal is another tool that that allows designers to analyze board level thermal problems by performing thermal simulations. Both of these tools provide excellent integration with PADs.
PADs also comes with its own auto-router as an option. While it is not as powerful as its Cadence counterpart, it performs auto-routing of medium complexity with satisfactory results.
Like Cadence Allegro, PADs also has its disadvantages. First is its cost. Even though it is not as expensive as Cadence, one can end up paying tens of thousands of dollars for all its options. Secondly, it is not a very good tool in handling signal integrity issues.
Its design rules system is too simple and inflexible to carry out tasks required on high-speed boards. As an example, it is not an option to import the Chip pin-delay information into the tool as can be done in Allegro. This information can be quite important when dealing with timing analysis of high speed signals.
Thirdly, PADs is not effective at handling large number of layers. Having numerous copper layers in PADs can make the database size hefty and can become a burden on system’s resources.
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