Using simulation to build reliable high-speed embedded systems

Patrick Carrier, Mentor Graphics

February 19, 2013

Patrick Carrier, Mentor Graphics

High speed design has brought a set of design challenges that do not exist in lower speed designs, or exist at levels that don’t cause problems,. The ever-increasing clock speeds and edge rates have turned digital switching circuits into some rather good RF generators whichis not a good thing, of course! Other problems begin to manifest at higher speed as well: signal integrity problems due to impedance variations; power integrity problems that can cause switching failures or overheating.

There are two basic methods to ensure designs will function as intended and also meet EMI radiation requirements. The traditional method was to carefully follow established design rules and, through visual inspection, determine that the board adheres to those rules and is likely to function and pass EMI. Then a physical prototype is used to verify function and EMI compatibility. For lower-speed or less complex designs, this may still be adequate. But for complex and/or very high-speed designs, more assurance is needed.

Simulation is the second method of ensuring that designs meet requirements. Until recently, simulation was complicated and expensive, and usually required a specialist to execute it. The process often took overnight or even days.

Now new tools that are exceptionally easy to use can be integrated into design flows, taking data from the CAD system and running simulations. Tools are available to perform signal integrity (SI), power integrity (PI), and EMI checks using design rule checking (DRC). In this article, we examine EMI simulation and control, a common problem, as an example of how simulation can save time and cost by catching issues that would mean a design respin if a physical prototype was used. Figure 1 illustrates how simulation can provide both early prevention and early detection of problems that could be very costly.


Until processors began running in the hundreds of MHz and up, little attention was paid to EMI in most circuit designs. As clock speeds have increased to beyond 1 GHz, the fast edge rates on signals, coupled with the high volumes of low-cost electronic devices, have made electromagnetic compatibility issues extremely common.

Since 1982, the FCC has required that all electronic devices used in the United States pass standard EMI tests for radiated emissions. But even in devices that can pass the test some radiation remains, meaning EMI can reduce signal margins and increase susceptibility to outside noise. Most of these problems can be avoided simply by making sure all currents are travelling in a closed loop.

Visualizing return current involves a departure from the more intuitive notion of current travelling in a wire at DC (0 Hz) to thinking of current being transferred through electromagnetic fields at higher frequencies. Figure 2 shows a PCB trace and how its energy is into its reference planes through electromagnetic fields. The amount of energy transferred to the reference plane is proportional to the distance to each reference plane, as shown in the figure.



Whether the planes are at ground or a voltage plane, the trace will be coupling energy into its reference planes. The best case is if those planes happen to be the power and ground planes used by I/O buffers driving that trace, as this best accommodates a complete loop for the return current.

Using circuit theory to understand the current loop, it’s easiest to view the side of the trace and its reference planes using , illustrated in Figure 3. Chopping the trace into very short sections allows each section to have an associated inductance and capacitance per unit length. As the signal propagates through the trace, it is effectively charging up each of the LC circuits, and then moving on to the next one, charging that one up, and so on.



The inductance and capacitance are specified “per unit length”. Those inductance and capacitance values are determined by the propagation of fields between the trace and reference planes, and the values can be determined for trace structures using the HyperLynx field solver. In fact, field solvers are used to determine the trace impedance (the square root of L/C) and propagation delay (the square root of L*C).

With this model, it’s clear how current loops from the trace back onto the planes. In this example, since there are two reference planes, there are two loops in parallel. Within the trace, the current is usually referred to as incident current, and current in the planes is return current.