Using a PCIe over Cabling-based platform to create hybrid FPGA/virtual platform prototypes

Troy Scott, Synopsys

May 21, 2013

Troy Scott, SynopsysMay 21, 2013

In-context IP validation
FPGA-based prototypes are considered 'high-fidelity' because of the internal processing performance, on the order of 50-75 MHz (typical), coupled with the ability to be immersed in real-world environments with test equipment, radio interfaces, memory ICs, electro-mechanical transducers, etc.

This fidelity and ability to run a cycle-accurate DUT at high performance is attractive as a companion to virtual prototype simulations incorporating embedded CPUs running at very high MIPS performance while executing a firmware stack, embedded OS, and an application software layer. By linking a virtual and FPGA-based prototype together, a new prototyping category is created, referred to as 'hybrid'.

The motivation for hybrid prototypes is largely driven by engineering and program management as a way to accelerate the availability of prototypes. This is accomplished by mixing the SoC block prototypes (virtual or FPGA) that are most readily available to the development team.

Hybrid prototypes are employed for a variety of hardware/software validation scenarios:

  • Rapid bring-up by blending pre-existing IP from legacy ASIC/SoC projects or commercial IP with a virtual model or user application, which are typically far faster to develop
  • Use a virtual model for a complex processor subsystem while peripherals are allocated to FPGAs to provide superior MIPS throughput using loosely-timed models and the cycle accuracy and high fidelity of real world hardware I/Os
  • Start a new SoC entirely modeled in a virtual domain then incrementally substitute subsystems as RTL HDL becomes available

Consider the case where a virtual model delivered by an IP provider of an embedded processor is employed for the latest CPU and subsystem. This model is functionally equivalent to the release version, however RTL and physical IP are not available to SoC developers (perhaps due to schedule or licensing restrictions), making a virtual platform the only feasible way to start software development immediately.

Another important SoC block of this design is an HD video codec for which no SystemC transaction-level simulation model is available. While the codec may not be tremendously important for initial software development, higher order functions of the software stack do address a new display panel and the quality team would like to assess refresh rates and landscape-to-portrait orientation speed. The team decides to use the RTL from the previous codec design and implement into FPGAs to obtain accuracy and performance.

The team responsible for the prototype identifies the following project goals:
  • Deliver an operational prototype in under one month
  • Achieve prototype performance fast enough to make software development feasible
  • Validate new software drivers with actual SoC IP
  • Attach to real world streaming I/O to stress test SoC IP using benchmarking tools

These objectives reflect the reality of prototype development projects and the realism and sophistication of validation tests.

As a case study to measure the preparation effort and performance characteristics of a realistic system (Figure 4) partitioned between a SystemC model and FPGAs, we developed a hybrid prototype consisting of a virtual ARM Versatile Express uATX board utilizing ARM Cortex A9x2 CPUs implemented as SystemC/TLM, and a USB 3.0 device mode controller implemented in a HAPS-60 series FPGA-based prototyping system from RTL source.

To physically link the virtual model host workstation to the HAPS hardware motherboard, the UMRBus and PCIe plug-in board are used to establish the physical link and a low-latency communication layer. A Synopsys Transactor Library for AMBA is provided with software API for SystemC/TLM and synthesizable Verilog HDL for implementation into the Xilinx Virtex-6 FPGAs of the HAPS-60 series system. A HapsTrak daughterboard with a USB PHY device completes the physical system elements.

The virtual Versatile Express board provides a software stack composed of USB devices drivers, Linux OS and a file storage application. Connections between the virtual and FPGA prototype domains are via a single master and slave AXI 3 transactor for bus connections, and a GPIO transactor for interrupts.

We began the virtual prototype project with the Versatile Express uATX board reference design part of our Virtualizer Development Kit (VDK) Family for ARM Cortex processors. From within the Virtualizer platform editor interface, the TLM 2.0 model of the USB 3.0 block was replaced by AMBA AXI transactors, a bus protocol-specific interface between the virtual and FPGA-based prototype.

Since the USB 3.0 had two interfaces - an initiator and a target - both an AXI master and a slave transactor was inserted. Interrupt output from the USB 3.0 device controller was replaced by a general purpose I/O (GPIO) transactor. The platform’s memory map and transactor parameters were configured to reflect the protocol details. The development required one day for platform assembly and one day for troubleshooting the configuration.

The FPGA-based prototype utilized a HAPS-62 system with an ASIC gate capacity of approximately 18 million as a host for the USB 3.0 device controller block; an HAPS daughter board with a USB PHY interface IC and physical connectors; and a UMRBus interface kit to connect to the host workstation running the virtual prototype. The preparation effort for the hardware flow required 3-5 days to assemble the platform and one day for troubleshooting the configuration. Given expert users of the Virtualizer and HAPS systems, the team was able to bring up the system in less than 2 weeks.

Figure 4. SoC design partition between virtual and FPGA-based prototypes

To demonstrate a real world validation scenario, the hybrid prototype is attached to a Windows 7 laptop with a USB 3.0 host port. The Windows OS auto-detects the new USB device and appears as a new volume to Windows Explorer. USB3-Read/Write benchmarks using the DiskBench application on a Windows 7 PC showed that reads achieved 0.515 MByte/sec and writes of 0.500 MByte/sec. Linux OS file mount time of the USB 3.0 mass storage device took about 1second. To illustrate the performance, a 60 MB MP4 movie was played at real-time speed on the Windows laptop.

ASIC/SoC development teams are maximizing the return from the investment in prototyping systems by taking advantage of FPGA-based prototypes with features for remote access from a host workstation. They are able to increase the variety and realism of hardware/software validation scenarios with reliable and high-performance PCIe-over-Cabling connectivity, APIs and logic for client/host communication, and bus protocol-specific transactors that allow the design team to segment the prototype between software and hardware-based hosts.

Data exchange links allow prototypes to communicate with custom user applications for system control and monitoring. Given a transaction-level interface, a new class of hybrid prototypes could potentially leverage the strengths of both FPGA and virtual prototyping abstractions.


1. FPGA-Based Prototyping Methodology Manual (FPMM), Best Practices in Design-For-Prototyping

2. Synopsys FPGA-Based Prototyping Solutions

3. Synopsys Virtual Prototyping Solutions

4. Synopsys Hybrid Prototyping Solutions

Troy Scott, product marketing manager, is responsible for FPGA-based prototyping software tools at Synopsys. He has 20 years of experience in the EDA and semiconductor industry. Before joining Synopsys he was a product manager at Lattice Semiconductor, where he worked to design and market FPGA design tools. His background includes HDL synthesis and simulation, SoC prototyping, and IP evaluation and marketing. He holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.

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