Migrating your embedded PCB design from DDR2/3 to DDR4 SDRAMs
PCB and embedded systems designers are scratching their heads these days, facing some uncertainty as they start mapping out the move from DDR3 SDRAM to DDR4. Routing DDR2 signals on a PCB was tough enough. But with DDR3 it proved to be even more difficult and challenging. The big question now is: will DDR4 be just as much of a challenge? More? Or less?
Double data rate synchronous dynamic random-access memory (DDR SDRAM) is the most commonly used class of memory integrated circuits used in today’s microprocessor-based systems. DDR SDRAM, also called DDR1 SDRAM, over the years was superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which is backward compatible with DDR1 SDRAM. As a result, DDR2 or DDR3 memory modules will not work in DDR1-equipped printed circuit boards. The trend continues with DDR4 and it is up to PCB designers to make it work.
To make the transition from earlier DDRAM versions to DDR4, it is important to review the main differences between DDR2 and DDR3 and find out what can be learned that will be useful transitioning printed circuit board designs to DDR4.
Schemes versus architectures
Industry discussions relating to DDR often talk about fly-by and point-to-point “architectures.” For the purposes of clarity in this article the main focus is on the I/O architecture of the DDR devices and discussions of specific uses within that context will use the word ‘scheme’. In this article, ‘fly-by schemes’ applies to termination only. When the term ‘architecture’ is used, it refers to I/O architecture.
Fly-by, as used in DDR3 devices, is a scheme by which to connect the command and address signals in series with each of the memory modules, along with appropriate termination at the end. The signals travelling in this topology reach different memory modules at different time intervals and encounter the input capacitive load of the memory modules in a delayed fashion.
DDR2 – DDR3 similarities and differences
The main differences between DDR2 and DDR3 are: Noise margins are far less for DDR3 than for DDR2. Clock routing in particular is critical here. DDR3 uses differential clocks and they need to be length-matched as well as impedance-controlled. The length of the clock signal has to be length-matched to the lengths of signals in the address and command group.
When length matching, the most important thing to keep in mind is the difference between the signal lengths within a given DDR byte lane and that of its strobe. So for DQS (Data Queue Strobe) and DM (Data Mask) lines the maximum deviation has to be ±/10 picoseconds. Translated into length, that’s around ±/50 mils on a PCB’s FR4 glass-reinforced epoxy laminate material.
This doesn’t allow much leeway when length-matching the signals. For many PCB and embedded designers, this is quite a challenge, especially when working with very tight spaces. The more cramped the space, the more difficult it is to match those lengths. Figure 1 shows length-matching for a DDR3 PCB layout.
With so many different types of signals intertwined in DDR3, the designer has to be both proactive and interactive when routing these signals. Once a signal is routed and goes out of spec with another trace, the designer has to go to the other trace to tune it. In the end, he or she must have a well designed system so that all trace lines and spacing are properly managed and lengths are matched with the groups. It is therefore very important to route the longest lane first.
Ideally, the goal is to have equal signal lengths in the address and command groups. Also, mismatched transmission lines to vias must be avoided. In most cases vias should not be used. The one exception is in PCBs that incorporate ball grid array (BGA) circuit packages.
Routing address and command signals in a daisy chain topology represents a major change between DDR2 and DDR3 routing. Maximum length between the first SDRAM and the last one in the chain must not be more than five inches.
Impact of DDR2/DDR3 differences on PCB designs
The main differences between DDR2 and DDR3 is that DDR3 has a faster frequency, improved power delivery, greater package reliability, improved pin placement, and fly-by termination. DDR2’s rated speed is specified at 400 to 800 megabits per second (Mbps) whereas DDR3’s doubles that to 800 to 1600 Mbps.
This means that routing requirements for byte lane, clock, and address and command signals is extremely critical. For that high level of performance, tighter tolerances are demanded including tighter control of length-matching, crosstalk, and electromagnetic interference (EMI). As an example, data bits within a byte lane should be 10 mils, and between byte lanes it should be within half an inch.
Thanks to more advanced packaging, there are more power and ground balls on a DDR3 memory ball-grid array (BGA) package than on DDR2. This not only improves power delivery, but also helps to improve signal quality and reduce signal loops. With the increased number of ground and power connections, ground bounce and Vcc SAG (signal after ground) are reduced. Ground bounce occurs on the ground pin, while Vcc SAG happens on the power pin. Both can occur when there are high inductance connections from the chip to ground, thus causing a spike on the reference planes when the signal switches.
Another plus is that the advanced BGA has two features that provides greater reliability. First, it has more balls and is fully populated. Second, improved I/O pin placement produces less skew between the BGA ball and inside wire bond distances and thus provides tighter timing of critical signals
Finally, as discussed earlier, DDDR3 comes with the fly-by termination scheme versus DDR2’s parallel termination. Fly-by provides a much higher level of signal integrity; and the eye diagram is more controlled. Fly-by also reduces stubs on the termination, resulting in better signal integrity on critical signals. Figure 2 shows the fly-by termination topology.
Because DDR3’s fly-by termination is used with clocks and command and address bus signals, it reduces simultaneous switching noise (SSN) by deliberately causing flight-time skew between the data and strobes at every DRAM as the clock, address, and command signals traverse the dual-in line memory module (DIMM).