Tear Down: Handheld phone/PC offers full-size laptop features

Richard Nass

September 10, 2007

Richard Nass

In reality, the data is buffered to local memory, then output to a larger SDRAM, which has a direct connection to the 8150. Streaming occurs between the devices at a rate high enough to maintain 60 frames/s.

The 8150 also offers error correction and checking (ECC) in case any frames become corrupt or out of sync. The part actually looks at each frame, and if there's an error, it can skip ahead and grab the next frame.

This turned out to be a key component of the design, as data would occasionally get shifted at the output, causing the video to flicker. While the source of this problem was never actually determined, the ECC cleared it up. It could have been caused by noise on the board or timing issues.

Part way through the design, the HTC designers, who were based in Taiwan, realized that there were too many clocks (oscillators) on the board. When the QuickLogic engineers got wind of this issue, they came to HTC's aid, helping to reduce that number of clocks. For example, a 70-MHz clock was needed to run the SDRAM. That could be handled in the 8150, with a quick conversion. Hence, HTC didn't need an extra oscillator just to regulate the SDRAM.

There were some alternatives to the 8150, but each seemed to carry a tradeoff that the HTC designers weren't willing to make. For example, some of the other programmable devices offered more features, but they required more power. Or they could have gone to a more full-function decoder, but it came with more features that were required, hence higher cost.

Another alternative would have been to handle the X–Y swap in software. But the performance hit was beyond what the designers were willing to take, especially with the required frame rate.

The 8150 device includes the ability to selectively stop all display subsystem clocks and shut down the attached SDRAM, thereby reducing the system's overall power consumption. It also operates in a very low power (VLP) mode, whereby it enters a quiescent state, drawing just 2.2 µA at 1.8 V.

In VLP mode, all internal register and FIFO bits are retained, and the device can be "woken up" by the host processor within 250 µs. In operational (active) mode, the 8150 draws less than 30 mA at 1.8 V.

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The host CPU communicates with the FPGA over the I²C bus. Using this interface, the CPU can configure the design with the proper output timing and format, and configure the power management features.

The 8150 could have also been used to handle some of the connectivity. For example, the USB interface uses a legacy 1.1 connection. They could have easily upgraded to 2.0 with little added cost using the 8150.

There are also a pair of Xilinx CoolRunner II (2C128) CPLDs on the board to handle some of the control and glue logic. These parts offer 3,000 system gates and 128 macrocells.

Richard Nass is editor in chief of Embedded Systems Design magazine and editorial director of the Embedded Systems Conference. He can be reached at rnass@cmp.com.

Reference:

QuickLogic Corp. "QuickLogic X/Y Swap Design for Simultaneous LCD and TV-Out Display in Handheld Electronic Devices," white paper, 2007.