The ABC's of A-D converter latency
Low-level, sensor signals often generate slow-moving DC signals. For these types of sensors, the delta-sigma, analog-to-digital converter (D–S ADC) eliminates most of the analog input circuitry by providing a high-resolution, low-noise solution. Some systems have multiple sensors, all of which are generating low-frequency signals. In this situation you may need a high-resolution, low-noise ADC that has a multiplexer at its input. An automotive-diagnostic application is an example of a multiplexed sensor system, where numerous small-signal, sensors monitor temperature, tire pressure, airbag readiness, and so forth (see Figure 1).
Examples of other sensor-input, multiplexed systems are found in industrial controls, medical, avionics, and process-control applications. Even though the sensors at the input of the multiplexer in these systems present low-frequency (nearly DC) signals, switching from channel-to-channel creates the need for an ADC that is capable of a high-speed response.
In the multiplexed sensor application circuit in Figure 1, the ADC must be a converter that has multiple channels, zero latency (zero-cycle latency), and low-latency time (settling time). This system requires fully settled output data from each conversion. Before we design such a system we must know something about the signals we wish to digitize. Are they DC signals--perhaps from a number of thermistors or thermocouples? Or are they AC signals, such as two microphones capturing a stereo signal? Or is a combination of both types of signals in the circuit--perhaps the system needs to monitor power supply voltages while it measures power-line frequency as well?
The description of ADC latency implies that a full-scale input signal occurs followed by fully settled output result. This environment is similar to the signal that is presented to the ADC in a multiplexer application. When it comes to A-D converters, there are two types of latency: cycle latency and latency time.
Cycle latency is equal to the number of complete data cycles between the initiation of the input signal conversion and the availability of the corresponding output data. The unit of measure for this type of latency is (n)-cycle latency, where n is a whole number. Cycle latency can be equal to zero if a fully settled conversion is completed before the start of the next cycle. As we will see, the successive approximation register (SAR) ADC is capable of 0-cycle latency as are many D–S ADC.