Adding bidirectional I2C digital isolation to your embedded design
This "Product How-To" article focuses how to use a certain product in an embedded system and is written by a company representative.
Historically, designers have used opto- couplers for I2C isolation. These circuits are somewhat complex, sensitive to bus capacitance and limited in speed. They are also not compatible with high speed digital isolators having standard CMOS input levels.
This design idea shows how to convert a standard high speed digital isolator to a bidirectional I2C isolator. In addition to being compatible with digital isolators, the circuit is simpler than previous published solutions, completely insensitive to bus capacitance and it can easily support the standard 400KHz maximum I2C bus rate.
Standard I2C SDA and SCL signals are driven by open drain drivers. In all cases, SDA can be driven by any device on the bus so that the SDA bus wire communicates information from the I2C master to the slaves and from the slaves to the master. That is, the data transfer is bi-directional. In some cases, the SCL only has a driver for the I2C master.
However, in many cases such as multiple I2C masters or if the slave needs to stretch SCL by holding it low while it retrieves data then the SCL line must also be bi-directional.
For the wires that need to be bidirectional, if digital isolators are inserted there are several problems; the isolators must be open drain, and there is a latch up condition that can occur. If, for example, the side A driver pulls low then isolator A pulls low on side B.
This causes isolator B to pull low on side A and the circuit latches with both isolators pulling low. The open drain problem is easily solved by putting a Schottky diode in series with the isolator output. However, the latch up problem is much more difficult to solve.
Previous attempts to solve this problem have used diodes inherent to the opto-coupler input and additional circuitry to avoid the latch-up condition. Some of these approaches are sensitive to bus capacitance.
They tend to be slow due to the slow response of the opto-couplers. Finally, when higher speed digital isolators with standard CMOS input levels are used, the circuit tricks using the diode input of the opto-couplers no longer apply.Circuit using digital isolators
The full circuit using a Silicon Laboratories, Inc. Si8442 high speed isolator is show in Figure 1 below. The circuit assumes 1K pull up resistors on the SCL and SDA lines. It can be easily adjusted for other bus pull up resistors. This circuit has been tested with Silicon Laboratories, Inc. C8051Fxxx series MCUs at a bus speed of approximately 300KHz including bus transactions which require SCL clock stretching.
|Figure 1: Diodes D1A, B and D2A, b convert the push-pull output of the Si8442 to open drain.|
The latchup problem described above is solved by using a comparator to sense whether the non-isolated side (side A) is causing the low on the isolated side (side B). Transistors Q1 and Q2 act as the comparators. If the low on side B is caused by low on side A, Q1 or Q2 will not turn on due the drop across diodes D2A,B and R1 or R2 and the low is not propagated back to side A breaking the latch condition.
If the low on side B is caused by the open drain driver on side B, Q1 and Q2 do turn on and the low is propagated. Note that the comparator circuit only needs to be used on one side, and could be used on either side A or side B. The voltage levels on Side A are completely compatible with I2C requirements and there is no special consideration for the side without the comparator circuit.
For side B, with the comparator circuit, the output of the isolator should not turn on the comparator but the open drain driver must turn on the comparator. The threshold of the comparators is set by the voltage dividers R3,R4 and R6,R7. Diodes D3A,B provide temperature compensation to match diodes D2A,B.
With the component values shown, the comparator threshold is approximately 0.28V. The schottky clamp pulls down to approximately 0.5V and the open drain driver pulls to typically 0.1V so the comparator threshold is well centred between these values.
If the bus pull up resistors are not 1K , the Vdd voltage is not 3.3V or if the driver on the side with the comparator cannot pull below 0.2V, the circuit will need to be adjusted. The pull down from the isolator (as determined by diode D2 and R1 or R2) must be adjusted to be compatible with the logic low of the devices connected to the bus on side B.
The comparator threshold is set by D3 (to track D2) and the voltage divider R3/R4 or R6/R7. The comparator threshold is adjusted to centre between the pull down of the isolator circuit and the pull down of the other I2C circuits on the I2C bus on side B.Circuit performance
The propagation delay from side A (non-isolated side) to side B (isolated side) introduced by the isolator circuit is negligible (<50nsec) for both rising and falling edges. This is because in this direction, the comparator is not in the path and introduces no delay.
For the falling edge, the delay is approximately 50nsec as the transistor switches on. For the rising edge there is a delay of approximately 250nsec as the transistor switches off. Also note that in this case, the final rise of the input waveform is delayed so that the skew as the waveforms cross a typical 1V CMOS logic threshold is quite small.
The added delay introduced by this circuit is compatible with I2C or SMBus operation at speeds up to 400KHz. Therefore, using a digital isolator for I2C isolation provides many benefits to the designer over the traditional implementations.
John Gammel is with Silicon Laboratories.