Design Con 2015

Think it - Draw it - Build it

Mark Saunders

June 15, 2010

Mark SaundersJune 15, 2010

Embedded systems designers deserve better than the feature-lacking point-tools available today. Embedded designs should be more than a collection of microcontrollers and discrete components, pulled together by board design tools and software development environments that are not aware of each other presence, let alone integrated together.

Programmable devices are not new. Embedded software is older than most of us! And a lot of embedded design is highly focused on specific interaction between the software and peripherals. So why do we still not have tools that bring all this together and make our lives easier and more productive?

In September 2009, Cypress Semiconductor introduced the PSoC Creator embedded design tool for its new PSoC 3 and PSoC 5 programmable system-on-chip architectures to address this question. PSoC Creator integrates support for PSoC programmable hardware with a full-featured software IDE.

It abstracts away the hardware so you do not need to be an expert on the device you are using or the inner workings of peripherals you program it with. It routes on-chip connections and I/O automatically. And it generates APIs for the peripherals and on-chip functions, which are known as components, to ensure error-free interaction from software.

The nuts and bolts of PSoC Creator
Once you press the build button PSoC Creator uses a number of tools to convert your designs and application code into a flash-able image.

Elaboration. All designs are hierarchical and so the first thing that needs to happen is elaboration; the TopDesign is parsed for all the constituent components and those, in turn, are parsed, all the way down the line. The result is effectively a flattened-out (non-hierarchical) version of your design.

HDL Generation. HDL (Hardware Description Language) generation is the next step. At the lowest level all components are implemented in Verilog. The flattened out design is translated into an HDL netlist.

Synthesis. This is a two-step process; logical and physical. The logical step optimizes the design (i.e. removes unused elements) and generates a simpler register-transfer-level (RTL) representation of (primitive) components and Boolean equations. The physical step identifies and maps the primitives to physical hardware in the device and then connects signals through the “switch fabric” or routing network.

API Generation. Next comes the generation of boot code and API files and their addition to the Workspace Explorer. API files are defined as part of the component and the generated files use the name of the component instance as a prefix so that each instance has its own APIs (no pointers to RAM-based data structures).

Compilation and Linking. PSoC 3 and PSoC 5 use industry-standard CPU architectures; 8051 and ARM Cortex-M3, respectively, so that you can choose your favorite compiler. For PSoC 3, a fully-functional Keil CA51 compiler package is included, free of charge, in the distribution.

To get the best levels of optimization you can upgrade by purchasing the professional version from Keil. For PSoC 5 the GNU GCC compiler is included. Also supported is the RealView compiler, available from ARM Ltd.

Hex File Generation. The final step in the process is the generation of the flash image in a hex file. This file includes the software application and bitstream that was generated by the physical synthesis of the design.

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