USB 3.0: Delivering superspeed with 25% lower power

Mike Micheletti

November 9, 2010

Mike Micheletti

USB 3.0: Designed for power efficiency
Recognizing that continued adoption of USB will require improved power efficiency, the USB Implementers Forum (USB-IF) has made power management a cornerstone to its next generation interface, SuperSpeed USB. For backwards compatibility, USB 3.0 devices are required to support both 2.0 and 3.0 link speeds. USB 3.0 devices will maintain separate controllers and physical layers for high/full speed and superspeed links. To ensure power savings gained while operating in USB 3.0 mode are not lost when 3.0 hosts are connected to legacy 2.0 devices, all USB 3.0 ports (host and device) are now required to support the LPM feature above when operating at high/full speed. Correct power-management operation in both legacy USB 2.0 mode as well as superspeed mode will be verified during USB 3.0 logo certification.

SuperSpeed USB uses dual simplex differential signaling operating at 5 GHz frequency to provide a 10x performance increase over high-speed USB. The higher power required to drive the 5 GHz signaling in superspeed mode is more than offset by the improved efficiency of 3.0 data transfers. The USB-IF estimates the system power necessary to complete a 20-MB superspeed data transfer will be 25% lower when compared with high-speed mode. This is possible because several architectural issues that hampered USB 2.0 power efficiency have been enhanced in the USB 3.0 specification below:

• Elimination of device polling by allowing devices to asynchronously signal when they need service from the host.
• The ability for device ports to initiate low-power states.
• The ability for device ports to remove power from all or portions of their circuitry (function level suspend).
• The ability to use data streaming for bulk transfers.
• More efficient token/data/handshake sequence.
• The addition of packet routing eliminates the need to broadcast packets to all endpoints downstream from hubs.

In addition to these changes, USB 3.0 improves efficiency by implementing power management at the link layer to provide greater speed and precision in managing power consumption. Figure 1 shows the power savings when using superspeed data transfer.


Click on image to enlarge.
Table 2 outlines the four power states in USB 3.0. Each state incrementally lowers power use while increasing the allowed exit latency. This method provides a more adaptive power-management model that uses timers and link-state awareness to reduce power use. Although the specifics of how devices will lower their power draw are left to the vendor, Table 2 outlines the link states defined by the USB 3.0 specification.


Click on image to enlarge.
Most early 3.0 devices rely on inactivity timers to initiate entry into the U1 state. In the U1 state, these devices will typically reduce power to their SuperSpeed PHY. These devices will progressively lower power to other parts of the interface as the inactively period increases. In some cases, host ports will immediately request transition to the most aggressive power suspend state (U3) during idle periods. This more rigid approach to lowering power draw is generally initiated by higher layers and is based on expected usage patterns for specific device classes. USB 3.0 also preserves function-suspend features from USB 2.0 allowing individual functions to be placed into a lower power state. The remainder of this article explores the SuperSpeed power-management model and the power-state transitions required by the USB 3.0 specification.