USB 3.0: Delivering superspeed with 25% lower power
USB 3.0 offers new opportunities to boost battery life for both host and endpoint functions thanks to comprehensive power management features that operate autonomously at the hardware level.
The desire to extend battery life in the fast growing mobile computing market has placed a new spotlight on power management within portable systems. Developers of laptops, netbooks, smart phones, and tablets now scrutinize every amp of power usage at the system level in their drive for better power efficiency. The introduction of USB 3.0 brings new opportunities to boost battery life for both host and endpoint functions thanks to comprehensive power-management features that operate autonomously at the hardware level.
Designed to overcome the drawbacks of the Advanced Power Management (APM) model, the Advanced Configuration and Power Interface, or ACPI, was introduced in 1997. The specification brings some level of power awareness to the BIOS, system hardware and software. ACPI relies on tables in the BIOS to define the power modes for individual peripherals. The operating system then uses these definitions to decide when to switch a device, or the entire system, from one power state to another. USB 2.0 has supported this software-based approach relying on suspend-resume commands to place the universal serial bus in a power-reduced state. However, these ACPI-based implementations have been plagued by stability and latency issues.
Implementing an effective power-management policy for interfaces such as USB presents additional challenges. USB is one of the few peripheral buses that allow different types of devices with varying usage frequencies to attach simultaneously. Many of these USB devices experience extended periods of idle. In addition, developers must contend with the growing popularity of devices that draw power or recharge batteries over USB.
The USB 2.0 power-management model was enhanced with the introduction of Link Power Management (LPM) in the EHCI specification 1.1. The new LPM transaction is similar to the existing USB 2.0 suspend/resume capability, however—it defines a mechanism for faster transition of a root port from an enabled state (L0) to a new sleep state (L1). Implementing LPM requires changes at both the chip and software layers, which have slowed market adoption. Table 1 outlines the LPM entry and exit timing windows.
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