Teaching old dogs new serial I/O tricks on CompactPCI
Making a whole new connection to serial I/O
Maintaining compatibility with the original CompactPCI mechanics was an important goal for both the CompactPCI PlusIO and the CompactPCI Serial specifications. But in order to achieve the higher level demands of serial communications, something had to change along the way. That “something” was the board connector.
The heart of the change outlined in PICMG 2.30 is an Ultra Hard Metric (UHM) connector with specific features to accommodate the performance demands of high-speed serial communications signals. Yet, that newly specified UHM connector remains physically compatible to mate with the hard metric headers currently used in the original CompactPCI system backplanes, so it can work in legacy systems.
Because the hard metric headers could not support high-speed differential signals like PCI Express or SATA, the UHM connector incorporates specific physical features to accommodate the needs of the higher data transfer speeds – up to 5 Gbit per second – without crosstalk. These include individually shielded pins as well as 100 Ohm impedance suited for transmitting single-ended as well as differential signals. (Figure 2 below.)
Figure 2. UHMconnector
New options on the horizon.
With both CompactPCI PlusIO and CompactPCI Serial already adopted, the embedded industry has already seen the introduction of commercially available boards for immediate implementation.
Where CompactPCI PlusIO is used for migrating legacy systems to serial connections, CompactPCI Serial is implemented for new systems designs built solely on serial technology, while remaining backward compatible to older versions of CompactPCI.
The key advantages of CompactPCI Serial are that it is based on proven mechanics, can be mastered easily and is both reliable and robust – providing a high-tech solution with low cost and minimal overhead.
CompactPCI Serial is the only standard for modular computers that unites PCI Express, Ethernet, SATA and USB 3.0 on the backplane. The star topology architecture in the CPCI-S.0 specification simplifies the cost and effort required for implementation by eliminating the need for additional hardware like switches, bridges or fabrics.
The CPU chipset at the heart of the system controls peripheral devices and components through point-to-point connections. This allows high data rates without forcing any device to concede bandwidth to another. System designers have flexibility in how they choose to implement the new connectivity.
One option is a standard, fully-CompactPCI Serial system with nine slots via a one-slot CPU, since the CPU slot can accommodate eight peripheral slots. A dual-slot CPU allows a designer to combine both CompactPCI Serial and CompactPCI PlusIO to create a hybrid system. Another iteration of a hybris system is connecting a CompactPCI system to Serial system via card pair. A dual-slot CPU system can include support for:
* 8 x PCI Express (also gen.3) (for local extensions)
* 7 x 4 lane interfaces
* 2 x8 lanes interface fat pipe with 2 dedicated I²C high-speed buses for the fat pipe
* Optional Serial RapidIO (SRIO)
* 8 x SATA/SAS (for hard drives and RAIDs)
* Supported by SGPIO bus (SFF-8485 specification) for hot-plug capability
* 8 x USB (also 3.0) (for hot-pluggable mobile I/O as a legacy interface)
* 8 x Ethernet (also 10 Gb) (for computer-to-computer connections)
Optional hot-plug support by one dedicated I²C bus and optional IPMI support by one dedicated I²C bus are also available. The accommodation of USB 3.0 interfaces supporting Gigabit/second bandwidth offers ten times the bandwidth of the USB 2.0 format supported by CompactPCI PlusIO. (See Figure 3a, above and Figure 3b below.)
Figure 3b. CPCIPlus_Mesh
As shown, each CPCI-S.0 peripheral slot has the ability to support:
• 1 x PCI Express interface
• 1 x SATA (supported by a dedicated SGPIO bus – SFF-8485 specification)
• 1 x USB 2.0
• 1 x USB 3.0
• Up to 8 Ethernet interfaces
• Geographical addressing
For simplicity and versatility, every slot defines identical interfaces, with the CPU distributing the signals to each of the eight peripheral slots via the backplane. CompactPCI Serial’s star architecture ensures that one system slot can control up to eight peripheral slots, with no bridges, switched fabrics or special backplanes required.
One dedicated PCI Express fat pipe is provided for high-end applications and two of the slots support an additional PCIExpress x8. Otherwise all peripheral slots are equal in the sense that any board can be plugged into any slot.
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