Expanding emulation’s reach with virtual devices
Virtual devices are also very fast. They are not faster than ICE, but they are just as fast. Emulation speed is typically limited by how fast a design can run in the emulator, not by the virtual device or the communication to the workstation.
To demonstrate this, we can take a Veloce customer’s experience using the Mentor Graphics VirtuaLAB Ethernet capability to generate Ethernet traffic to exercise an edge router chip. They activated twelve 10G ports on their chip, with a million packets passing through each port, for 12 million packets total. It took 45 seconds to emulate it on Veloce. The customer estimated that it would take about thirty days to run a single port, with one million packets, in simulation. Doing all twelve ports would have been impractical to simulate.
The customer’s edge router chip was configured by their router control application running on a Linux workstation, just like their routers are configured by the same application. Via the co-model host, they linked the Linux box to the router chip design in the emulator.
It looked exactly like running their chip in the lab, except that it was all done virtually and done long before the hardware prototypes or silicon was available. The chip was compiled into the emulator, and the virtual Ethernet capability was shared between the Ethernet transactors in Veloce—written in RTL and compiled in the emulator—and a traffic generator on the co-model host. This setup allowed them to do all kinds of analysis, make modifications, analyze performance and bottlenecks, and fix their chip months before silicon.
To do the same thing with the classic, physical ICE approach they would need to purchase Ethernet testers, which are fairly expensive. Then they would need a bank of speed bridges to act as the speed adapters between the Ethernet testers and the emulator.
In order to support multiple users, as they could easily do with a virtual lab (Figure 4, below) they would have to duplicate that entire environment of Ethernet testers, speed bridges, and cables. When designs start getting up to 24, 48, 96, and even 128 ports, it becomes impractical to do this via ICE. The virtual lab is a much better approach.
Click on image to enlarge.
Another benefit of the virtual approach pertains to how simulators and emulators support a capability called save and restore, or check point restart. With check point restart, a user does not have to re-emulate their RTOS every time they want to check out the device drivers and applications they wrote— as the RTOS only needs to be debugged once and it can take from one to ten hours to emulate the RTOS boot just to get to the device drivers.
However, if physical peripherals are connected to the emulator via the classic in-circuit approach, they are not going to be able to checkpoint their state and they are not going to be able to restore or restart their state. Physical peripherals simply cannot save register and restore states.
Virtual lab peripherals support save and restore of the complete environment, including the peripherals connected to the SoC as it sits in the emulator. This makes save and restore practical on a full-chip, with peripherals, at the emulation level.
Emulation Around the Clock, Around the World
A virtual lab emulation environment is very cost effective, providing simultaneous access to a single emulator for many software engineers. Virtual solutions provide accelerated simulation and software debug that increase verification productivity and design quality.
By delivering efficient multi-user support and data center compatibility, virtual peripherals will usher in emulation for companies large and small. Because a virtual emulation environment can be shared around the clock and around the world, it is now cost-effective for small and medium sized firms to use emulation. Indeed, with the virtual lab model, emulation’s time has finally come.
Jim Kenney has over 25 years of experience in hardware emulation and logic simulation and has spent the bulk of his career at Teradyne and Mentor Graphics Corporation. At Mentor Graphics, Jim had held responsibility for analog, digital, and mixed-signal simulation, hardware/software co-verification and hardware emulation. He is currently the Marketing Director for Mentor’s Emulation Division. Jim holds a BSEE from Clemson University.
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