Using magnetoresistive memory devices in embedded systems designsThe core operating structure of a magnetoresistive RAM (MRAM) device is a magnetic tunnel junction (MTJ).
The bit state is stored as the relative magnetization orientation of two magnetic layers in direct contact with a tunnel barrier, with an antiparallel orientation (high state) having a higher junction resistance than a parallel orientation (low state). The bit state is read out by passing a current through the junction and comparing the junction voltage to a known reference.
Freescale's MR2A16ATS35C 4Mbit MRAM is manufactured in a 0.18 micrometer six-metal process with a 256K x 16bit configuration, runs on a 3.3V supply and is available in a 44-pin TSOP type-II package.
Such an unusual part always catches our attention, so we couldn't resist looking inside to see how Freescale put it all together.
|Figure 1. The contacts seen at the center of the upper plate go to a common top electrode, and those at the top edge of each lower plate go down to an isolation (select) transistor in the substrate.|
The Freescale MRAM cell has multilayer MTJs placed diagonally between two high-current write line conductors, which are formed in metal 4 and metal 5, and arranged at right angles to each other. The chip has been delayered to expose an array of MTJ structures, showing the smaller top plates overlying the larger bottom plates (Figure 1, above).
We can just see the lower write lines under the array of junction plates. The contacts seen at the center of the upper plate go to a common top electrode, and those at the top edge of each lower plate go down to an isolation (select) transistor in the substrate.
|Figure 2. The device uses magnetoresistive tunneling across an insulating tunnel barrier, sandwiched between two SAF layers, with the top SAF layer a "free" layer and the bottom SAF a "fixed" reference layer.|
Figure 2 above illustrates the principle of operation of an MRAM cell. The device uses magnetoresistive tunneling across an insulating tunnel barrier, sandwiched between two synthetic antiferromagnetic (SAF) layers. The top SAF layer is "free" (i.e. its magnetic moment can be programmed), and the bottom SAF is a "fixed" (not programmable) reference layer.
Figure 3 below shows the lower M4 write lines in cross-section and a linear section of an upper M5 write line, with the MTJ structure in between (There are some voids from sample preparation in this image.).
|Figure 3. Shown is the lower M4 write lines in cross-section and a linear section of an upper M5 write line, with the magnetic tunnel junction structure in between.|
Multiple layer structure
Both the top and bottom SAF layers are actually three sublayers, two ferromagnetic layers separated by a non-magnetic spacer; the free ferromagnetic sublayers use a magnetically programmable material with almost balanced magnetic moments.
This allows the magnetic moments to rotate like a pair of linked "clock hands" when the magnetic field is applied. The tunnel barrier is aluminum oxide. The transmission electron microscopy image in Figure 4 below shows the multiple layer structure.
|Figure 4. Both the top and bottom SAF layers are actually three sublayers, two ferromagnetic layers separated by a non-magnetic spacer; the free ferromagnetic sublayers use a magnetically programmable material with almost balanced magnetic moments.|
The use of this type of structure - in its diagonal orientation - allows the magnetic moments to be toggled 180° using the same two-phase pulse sequence regardless of state, using both write lines. This requires a pre-read to see if a write sequence is needed, but protects the datum state from a single pulse on either one of the write lines (Figure 5 below).
The write lines themselves have some interesting structural quirks to optimize the magnetic coupling to the MTJ. Not the least interesting is that they are made of copper.
|Figure 5. The write lines themselves have some interesting structural quirks to optimize the magnetic coupling to the MTJ.|
Meanwhile, the bond pads and lower metal layers are the conventional aluminum consistent with the 0.18µm process. This is presumed to allow higher current density, to give a higher magnetic field and keep the cell pitch down.
The inlaid damascene structure also aids the use of magnetically permeable cladding layers, which concentrate the magnetic fields - Freescale claimed double the magnetic flux when these layers were added.
The cladding in the bottom write line focuses the magnetic field upwards into the tunnel junction. This is elegantly achieved by adding a nickel-iron (NiFe) layer to the barrier layer structure of the damascene line (Figure 6, below).
|Figure 6. The NiFe is laid down as an outer barrier layer, and then the usual Ta-based barrier before filling the trench with copper.|
The NiFe is laid down as an outer barrier layer, and then the usual tantalum (Ta)-based barrier before filling the trench with copper.
The upper write line is more difficult to make. This is because to focus the field down on to the MTJ, we need to have the cladding on the top and sides of the line (Figure 2).
Figure 7 below illustrates how Freescale achieved this: they put down a Ta barrier layer followed by the NiFe layer on the bottom and sidewalls of the trench. Then, the NiFe is sputtered away from the trench bottom and another Ta barrier layer is deposited.
The trench is filled with copper and planarized as usual, and nitride and oxide metal cap layers are deposited. These are masked and etched to expose the top of the M5 copper in the memory array. A second set of NiFe and Ta layers are deposited, and then polished back to remove the excess and isolate the lines, leaving "wings" at each line edge.
|Figure 7. Freescale put down a Ta barrier layer followed by the NiFe layer on the bottom and sidewalls of the trench. Then, the NiFe is sputtered away from the trench bottom and another Ta barrier layer is deposited.|
It's a relatively complex process, but it achieves the desired end. That covers the basics of the MTJ. With the lower metal levels being aluminum, and M4 and M5 copper, the device is one of the few parts with a true hybrid metallization structure, as distinct from the copper metal with Al bond pads in most 130nm and smaller parts.
This is a clue to the fab history of the part. When we looked at the front-end structure (i.e. transistors + M1 " M3), it looked very much like Taiwan Semiconductor Manufacturing Co. Ltd's 0.18 micrometer process that we've seen in other devices. Discreet inquiry revealed that the front-end was indeed outsourced to TSMC, and then the wafers were shipped back to Chandler to add the MRAM structure.
According to Freescale, the major advantage of this MRAM technology is that it is a back-end addition to conventional CMOS and is thus suitable for embedded use. This fab sequence would seem to be a clear demonstration of that statement.
As a manufacturing strategy, I think it also makes a lot of sense. It keeps the wafer cost down to foundry levels and also allows tighter inventory control for a speculative product launch - keep a stock of front-end wafers and only add the back-end as needed by order volume.
The MRAM cell size of 1.3 square micrometers compares well with SRAM cell sizes of that generation. One of the target markets is battery- backed SRAM storage used for applications such as data logging, and the device is packaged with an SRAM-compatible pinout.
With this part, Freescale has come up with a technology that could have some disadvantages in terms of price and performance. However, as a solution requiring zero power to store data, it will find some applications in the automotive, aerospace and similar markets.
Dick James is Senior Technology
Advisor at Chipworks Inc. To read a PDF version of this story, go to "MRAM
puts new spin on process, fab strategy."
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