How to manage power in capacitive touch sensing designs: Part 1
Capacitive touch sensing is replacing mechanical switches and push buttons in a wide variety of applications. Many battery-powered, handheld, and portable electronics have adopted capacitive touch sensing user interfaces.
The power constraints of these devices, along with the constant focus on energy efficiency, has made low-power design critical in capacitive touch sensing applications. Some best practices for reducing power consumption in capacitive touch sensing applications include:
. Optimize the sensor parasitic capacitance (CP) with board layout best practices
. Use sleep mode and optimize the sensor report rate
. Vary the report rate based on finger touch events
. Use the priority rule to wake up from sleep mode
Optimize the sensor parasitic capacitance (CP) with board layout best practices
Capacitive touch sensors typically consist of copper pads connected to a capacitive sensing controller input pins via traces. Figure 1 shows a typical capacitive sensor including electric field coupling lines.
When a finger comes in contact with the overlay covering a sensor pad, it forms a simple parallel plate capacitor called finger capacitance (CF). Even without a finger touching the overlay, the capacitive sensing controller measures some parasitic capacitance (CP). CP is the sum of the distributed capacitance on the sensor. This includes the capacitance of the sensor pad due to its proximity to circuit ground, the trace connecting the capacitive sensing controller input pin and the sensor pad, vias, and the capacitive sensing controller input pin.
The capacitive sensing controller converts the capacitance measured at its input pin to digital counts using an A-to-D converter. The controller uses a DSP algorithm to continuously monitor the digital counts and identify increases in sensor capacitance due to a finger touch.
The main components of CP are trace capacitance and sensor capacitance. CP is a nonlinear function of the annular gap between the sensor pad and ground, the distance between the trace and ground, trace length and width, and the sensor pad diameter.
There is no simple relationship between CP and PCB layout features but, in general, increasing the annular gap and decreasing the trace length and width will reduce CP. Unfortunately, widening the gap between the sensor pad and ground will decrease noise immunity. To achieve optimal CP and noise immunity, follow the capacitive sensing controller manufacturer’s PCB layout best practices.