Unique input regulation loop simplifies solar panel battery charging

Jay Celani, Linear Technology Corp.

May 24, 2011

Jay Celani, Linear Technology Corp.

Figure 2 shows a 2A 2-cell LiFePO₄ battery charger with power path management. This circuit provides power to the system load from the battery when the solar panel is not adequately illuminated and directly from the solar panel when the power required for the system load is available. The input voltage regulation loop is programmed for a 17V peak power input panel. The charger uses C/10 termination, so the charge circuit is disabled when the required battery charge current falls below 200mA. This LT3652 charger also uses two LEDs that provide status and signal fault conditions. These binary-coded pins signal battery charging, standby or shutdown modes, battery temperature faults and bad battery faults.


The input voltage regulation point is programmed using a resistor divider from the panel output to the VIN_REG pin. Maximum output charge current is reduced as the voltage on the solar panel output collapses toward 17V, which corresponds to 2.7V on the VIN_REG pin. This servo loop thus acts to dynamically reduce the power requirements of the charger system to the maximum power that the panel can provide, maintaining solar panel power utilization close to 100%, as shown in Figure 3.


Want a better efficiency? Replace the blocking diode with a blocking FET
The LT3652 requires a blocking diode when used with battery voltages higher than 4.2V. The voltage drop across this diode creates a power loss term that reduces charging efficiency. This term can be greatly reduced by replacing the blocking diode with a P-channel FET, as shown in Figure 4.

Figure 4 shows a 3-cell LiFePO₄ 2A charger with a float voltage of 10.8V. This charger has an input voltage regulation threshold of 14.5V and is enabled by the SHDN pin when V_IN ≥ 13V. Charge cycle termination is controlled by a 3-hour timer cycle. The blocking diode normally used in series with the input supply for reverse voltage protection is replaced by a FET. A 10V Zener diode clamp is used to prevent exceeding the FET maximum V_GS. If the specified V_IN range does not exceed the maximum V_GS of the input FET, this clamp is not required.


During the high-current charging period of a normal charge cycle (I_CHG > C/10), the /CHRG status pin is held low. In the charger shown in Figure 4, this /CHRG signal is used to pull the gate of the blocking FET low, enabling a low-impedance power supply path that eliminates the blocking diode drop to improve conversion efficiency. Figure 5 shows that the addition of this blocking FET improves efficiency by 4% compared to operation with a blocking Schottky diode.

Figure 5: Comparative efficiencies for blocking Schottky diode vs blocking FET as battery voltage rises for 15V to 10.8V 3-cell LiFePO₄ charger

Should the timer be used for termination, the body diode of the FET provides a conduction path once charge currents of < C/10 is achieved, and the /CHRG pin becomes high-impedance. If desired, a blocking Schottky diode can be left in parallel with the blocking FET to improve conversion efficiency during the top-off portion of the timer-controlled charge cycle. Use of a FETKEY as the blocking element also increases top-off efficiency.