Tips about printed circuit board design: Part 1 - Dealing with harmful PCB effects

Walt Kester

December 6, 2010

Walt Kester

Signal Return Currents

Kirchoff’s Law tells us that at any point in a circuit the algebraic sum of the currents is zero. This tells us that all currents flow in circles and, particularly, that the return current must always be considered in analyzing a circuit, as is illustrated in Figure C.4 below.  In dealing with grounding issues, common human tendencies provide some insight into the way the correct thinking about the circuit can be helpful in analysis. Most engineers readily consider the ground return current, I, when they are considering a fully differential circuit.

However, in considering the more usual circuit case, where a single-ended signal is referred to “ground,” it is common to assume that all the points on the circuit diagram where ground sym­bols are found are at the same potential. Unfortunately, this happy circumstance “just ain’t necessarily so.”

 

Figure C.4: Kirchoff’s Law helps in analyzing voltage drops around a complete source/load coupled circuit.

This overly optimistic approach is illustrated in Figure C.5 below, where, if it really should exist, “infinite ground conductivity” would lead to zero ground voltage difference between source ground G1 and load ground G2. Unfortunately this approach isn’t a wise practice, and when we’re dealing with high precision circuits, it can lead to disasters.

 

Figure C.5: Unlike this optimistic diagram, it is unrealistic to assume infi nite conductivity between source/load grounds in a real-world system.

A more realistic approach to ground conductor integrity includes analysis of the impedance(s) involved and careful attention to minimizing spurious noise voltages. A more realistic model of a ground system is shown in Figure C.6 below. The signal return current flows in the complex impedance existing between ground points G1 and G2 as shown, giving rise to a voltage drop ∆V in this path.

But it is important to note that additional external currents, such as IEXT, may also flow in this same path. It is critical to understand that such currents may generate  uncorrelated noise voltages between G1 and G2 (dependent upon the current magnitude and relative ground impedance). Some portion of these undesired voltages may end up being seen at the signal’s load end, and they can have the potential to corrupt the signal being transmitted.

 

Figure C.6: A more realistic source-to-load grounding system view includes consideration of the impedance between G1 and G2, plus the effect of any nonsignal-related currents.

Grounding in Mixed Analog/Digital Systems

Today’s signal processing systems generally require mixed-signal devices such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) as well as fast digital signal processors (DSPs). Requirements for processing analog signals having wide dynamic ranges increases the importance of high-performance ADCs and DACs. Maintaining wide dynamic range with low noise in hostile digital environments is dependent upon using good high-speed circuit design techniques, including proper signal routing, decoupling, and grounding.

In the past, “high-precision, low-speed” circuits have generally been viewed differently than so-called “high-speed” circuits. With respect to ADCs and DACs, the sampling (or update) frequency has generally been used as the distinguishing speed criteria. However, the follow­ing two examples show that in practice, most of today’s signal processing ICs are really “high speed” and must therefore be treated as such in order to maintain high performance. This is certainly true of DSPs as well as ADCs and DACs.

All sampling ADCs (ADCs with an internal sample-and-hold circuit) suitable for signal processing applications operate with relatively high-speed clocks with fast rise and fall times (generally a few nanoseconds) and must be treated as high-speed devices, even though throughput rates may appear low. For example, a medium-speed 12-bit successive approxima­tion (SAR) ADC may operate on a 10 MHz internal clock, although the sampling rate is only 500 kSPS.

Sigma-delta (Σ-∆) ADCs also require high-speed clocks because of their high oversampling ratios. Even high-resolution, so-called “low-frequency” Σ-∆industrial measurement ADCs (having throughputs of 10 Hz to 7.5 kHz) operate on 5 MHz or higher clocks and offer resolu­tion to 24 bits (for example, the Analog Devices AD77xx series).

To further complicate the issue, mixed-signal ICs have both analog and digital ports, and because of this, much confusion has resulted with respect to proper grounding techniques. In addition, some mixed-signal ICs have relatively low digital currents, whereas others have high digital currents. In many cases, these two types must be treated differently with respect to optimum grounding.

Digital and analog design engineers tend to view mixed-signal devices from different perspec­tives, and the purpose of this section is to develop a general grounding philosophy that will work for most mixed signal devices, without having to know the specific details of their inter­nal circuits.

Ground and Power Planes

The importance of maintaining a low-impedance, large-area ground plane is critical to all analog circuits today. The ground plane not only acts as a low-impedance return path for decoupling high-frequency currents (caused by fast digital logic) but also minimizes EMI/RFI emissions.

Because of the shielding action of the ground plane, the circuit’s susceptibility to external EMI/RFI is also reduced. Ground planes also allow the transmission of high-speed digital or analog signals using transmission line techniques (microstrip or stripline) where controlled impedances are required.

The use of “buss wire” is totally unacceptable as a “ground” because of its impedance at the equivalent frequency of most logic transitions. For instance, #22 gauge wire has about 20 nH/ inch inductance. A transient current having a slew rate of 10 mA/ns created by a logic signal would develop an unwanted voltage drop of 200 mV at this frequency flowing through 1 inch of this wire:

 

For a signal having a 2 V peak-to-peak range, this translates into an error of about 200 mV, or 10% (approximate 3.5-bit accuracy). Even in all-digital circuits, this error would result in con­siderable degradation of logic noise margins.


Figure C.7: Digital currents fl owing in analog return path create error voltages

Figure C.7 above shows an illustration of a situation where the digital return current modulates the analog return current (top). The ground return wire inductance and resistance are shared between the analog and digital circuits, and this is what causes the interaction and resulting  error. A possible solution is to make the digital return current path flow directly to the GND REF, as shown in the bottom of the figure above.

This is the fundamental concept of a “star,” or single-point ground system. Implementing the true single-point ground in a system which contains multiple high-frequency return paths is difficult because the physical length of the individual return current wires will introduce parasitic resistance and inductance, which can make obtain­ing a low-impedance, high-frequency ground difficult.

In practice, the current returns must consist of large area ground planes for low impedance to high-frequency currents. Without a low-impedance ground plane, it is therefore almost impossible to avoid these shared imped­ances, especially at high frequencies.

All integrated circuit ground pins should be soldered directly to the low-impedance ground plane to minimize series inductance and resistance. The use of traditional IC sockets is not recommended with high-speed devices.

The extra inductance and capacitance of even “low­profile” sockets may corrupt the device performance by introducing unwanted shared paths. If sockets must be used with DIP packages, as in prototyping, individual “pin sockets” or “cage jacks” may be acceptable.

Both capped and uncapped versions of these pin sockets are avail­able (AMP part numbers 5-330808-3 and 5-330808-6). They have spring-loaded gold contacts that make good electrical and mechanical connection to the IC pins. Multiple insertions, how­ever, may degrade their performance.

Power supply pins should be decoupled directly to the ground plane using low-inductance ceramic surface-mount capacitors. If through-hole mounted ceramic capacitors must be used, their leads should be less than 1 mm. The ceramic capacitors should be located as close as pos­sible to the IC power pins. Ferrite beads may be also required for additional decoupling.