Embedded system timing analysis basics: Part 1 - Timing is essential
Just as in comedy, timing is essential to the success of a microcomputer design. Often it is quite possible to get one system functioning by simply interconnecting the various components. But it is significantly more difficult to be able to guarantee that many systems will work under the entire range of possible conditions that they may be exposed to.
There are many designs in production right now that have a number of unidentified failures due to the lack of a worst-case analysis of the design. When timing or loading problems show up in a design, they usually appear as intermittent failures or as sensitivity to power supply fluctuations, temperature changes, and so on.
A worst-case design takes into account all available information regarding the components to be used with respect to variations in performance. Even when all parameters are at their most adverse values, the worst-case design can still be proved to meet the specifications.
These variants may be due to changing manufacturing conditions, temperature, voltage, and other variables. Without performing a detailed analysis, there is no way of knowing if the design will work reliably under all operating conditions. It is much better to design reliability and simplicity of manufacturing into a product using worst-case design rules than to attempt to correct a problem after the design has been implemented.
With the emphasis that must be given to the quality of the final product, a designer is obligated to perform a detailed examination of the timing in a system. As is the case in most quality improvements, these efforts result in direct cost and saving time. This is clearly one of the places where the designer can have the greatest impact on overall product quality.
Timing Diagram Notation Conventions
Timing notation is illustrated in Figure 6.1 below. The timing notation used in manufacturers’ data sheets may vary from this notation but is usually very similar. It is also important to notice that although the diagrams are reasonably standard, there is a wide variation in the selection of symbols for each timing parameter.
Figure 6.1: Timing diagram notation as used in this article.
The purpose of timing analysis is to determine the sequence of events in each of the bus cycles so that we can delimit, among other things, the time available for each of the components to respond to changes. This time is compared to the requirements as specified in the manufacturers’ data sheets to determine whether they are compatible and by what margin.
The most important timing specifications for interfacing components to a bus-oriented design are:
• Rise/fall time
• Propagation delay time
• Setup time
• Hold time
• Tri-state enable and disable delays
• Pulse width
• Clock frequency
There are two general classes of logic: combinatorial and sequential. Combinatorial logic has no memory and its output is some logical function of its current inputs, after some delay. Examples of combinatorial logic include gates, buffers, inverters, multiplexers, and decoders. Sequential logic has memory, which means that its outputs are a function of both current and past inputs.
Examples of sequential logic are flip-flops, registers, microprocessors, and counters. There are two types of sequential logic. Synchronous logic is synchronized to change only when there is a clock transition. In contrast, asynchronous logic does not use a clock signal.
Almost all the logic used in a microcomputer design will either be unclocked asynchronous logic (gates, decoders) or clocked synchronous logic (counter, latch or microprocessor). Some types of devices are available in either form. Each of the timing specifications in the following discussion is described using simple logic devices as they are typically used in embedded computer designs.
Rise and Fall Times
The rise time of a signal is usually defined as the time required for a logic signal voltage to change from 20% to 80% of its final value. The fall time is from 80% to 20%, as shown in Figure 6.2 below. These times are also commonly defined by some manufacturers as the transitions between the 10% and 90% levels.
Figure 6.2. Rise and fall times of a signal
Propagation Delays. The propagation delay is the time it takes for a change at the input of a device to cause a change at the output. All devices—even wires—exhibit some propagation delay. Some devices do not have symmetrical delays for positive and negative transitions. In Figure 6.3 below, the propagation times for a high to low transition are shorter than for a low to high transition.
This asymmetrical delay is common for TTL and open collector and open drain outputs because they are better at sinking current than sourcing it. Thus, the load capacitance is charged more slowly when the current is being supplied from the weaker “high side” or pull-up device. Propagation delays are usually measured from the 50% amplitude points, as shown in Figure 6.3.
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