Combining FPGAs & Atom x86 CPUs for SBC design flexibility

Christine Van De Graaf

June 1, 2011

Christine Van De Graaf

Market snapshot of design obstacles
Historically, development of new x86 technology was driven by performance requirements. However more recently, an increasingly high degree of integration and energy efficiency have become increasingly prominent factors affecting broad market interest in x86.

For example, an industry-first performance-per-watt ratio has been achieved by the Intel Atom processor, manufactured in 45nm technology with a TDP of less than two watts at 1.6 GHz performance. Corresponding low power consumption has enabled fanless designs and completely closed housings that meet both space-constrained and rugged design requirements.

Based on these key factors, flexible x86 technology has become more deeply integrated into embedded applications. At the same time, more interfaces are moving away from chipsets with dedicated controllers, while nearly all of today’s relevant interfaces are pre-integrated in chipsets.

This convenience is somewhat counter to the needs of embedded design, as the deeper an embedded PC has to be embedded, the more dedicated and tailored the necessary interfaces become. A certain design cost and overhead results, as many of the available standard PC interfaces are no longer necessary to embedded designs.

Further, many industrial applications rely on the older, but proven, ISA bus in order to protect investments, yet new processors no longer provide support for the ISA interface. Processing advancements once required PCI to ISA implementations, which were more cost-effective than porting ISA-based I/O cards to PCI or PCI Express.

The latter was expensive and unwieldy, demanding additional space for add-on components. This is also a short-term design choice as PCI support is not anticipated as a long-term chipset feature.

With FPGAs, software and IP cores now take on a more predominant role in embedded computing at the hardware level. So, rather than using a chipset with pre-configured I/O support, designers can utilize IP to customize I/O with software in a single board solution.

Consider the example of a global application requiring industrial Panel PCs with country-specific field busses and an extremely competitive BOM. Diversification of this type commonly requires using extension components, a costly and time-intensive design approach.

A configurable interface would be an ideal alternative, including the option to implement all required field busses, and would allow OEMs to be highly competitive with a single, globally applicable hardware platform that relied on a minimum of components.

Occasional changes in interface standards, newly published specifications and adjustments to individual protocols are also challenges, and effect sustainability of an embedded design.

Carrying out a long-term design with standard components may mean having to permanently change the hardware design, which in turn can lead to significantly increased costs based on ongoing test and certification requirements.

The evolving x86
By combining an x86 CPU core with an FPGA, designers are able to access pure IP – increasing design flexibility and streamlining the process for new applications. Only the IP cores must be maintained, providing a sharp contrast to the more difficult process of managing a range of different controller components.

Integrating the most current x86 processors with FPGAs ensures high-performance, open platforms that can utilize dedicated I/Os for proprietary interfaces and other application-specific features.

The full functionality of the complete chipset can even be implemented directly by an FPGA. And perhaps most importantly, this design approach provides long life with long-term interface support available.

Today’s more complex embedded systems often have unique I/O requirements resulting from the diverse devices that are part of the overall system. The x86-FPGA combined platform is well-suited for these applications, handling compute-intensive calculations and offering the option of relieving processor function from the controller and still implementing full hardware-based system functionality.

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