Developing and building systems using OpenVPX Profiles
Identifying a Backplane
After reviewing topology needs, the system architect determines if a simple star architecture is needed, or whether a more complex central switched architecture might be required. Review of the backplane profiles will identify the standard backplanes.
Next step is to find out if they are actually available. Conversations with the board manufacturer or a packaging company will reveal which standard backplanes have been brought forward.
If not, typical lead times to have a backplane built to the standard are on the order of 10 to 16 weeks. Such backplanes can usually be added to a standard development chassis.
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Figure 4. Central switch star: single root, data plan –star architecture is typical with one SBC and eight carriers
Adding Temporary Pipes to a Backplane
Adding connections to an uncommitted backplane is a method to test an evolving topology. A way to do this is via off-the-shelf differential cables, organized as OpenVPX jumpers.
These cables can be made with wafer based connectors, organized as Ultra Thin, Thin and FAT Pipes, allowing a point-to-point connection to be added to the backplane. For instance, a PCIe x 4 connection can be added from an SBC Payload slot to a Peripheral slot to drive a required expansion connection.
Development in Steps
If the target application can’t be implemented via a released OpenVPX backplane, it is likely that parts of it can be implemented with an off-the-shelf backplane. If the end application requires tailoring, then a target application profile (TAP) must be developed.
Figure 5a below shows how two standard profiles can be used to begin development, with a notional view of a topology required when multiple FPGA payload cards are used in an application.
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Figure 5. A target application profile (a) modifies a standard backplane profile with an extension that specifies the interconnect needed to add the extended version of the management switch (b).
The TAP in Figure 5a extends BKP3-CEN-07-15.2.3-n, by adding expansion plane interconnect between 3U front end processor boards. Single board computers are connected via the data plane, and control plane to the 3U Switch.
The switch provides PCIe Gen 2 fabric on the data plane, and Gigabit Ethernet via UTPs on the control plane. An extended version of the SLT3-SWH-6F6U-14.4.1 switch profile shown in Figure 5b is included in the target application profile.
In summary, designing with OpenVPX requires the user to be sensitive to the unique I/O mapping of each backplane to be used. The specification has provided a means to identify module I/O specific to the fabric protocol used, and slot I/O as a general mapping of the I/O per slot, in order to allow unique interconnect of the slots defined by a backplane profile.
Care must be exercised in selecting the backplane, since the fabric interfaces support different bandwidths, thus requiring better materials as the bit rate is increased.
OpenVPX has provided a set of profiles, or recipes for implementing VPX-based systems. Variants of the existing backplane profiles are expected, and will be necessary to implement specific applications that can be described as Target Application Profiles.
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