Adding isolation to LVDS interfaces

May 03, 2016

CWatterson-May 03, 2016

Galvanic isolation of external interfaces is required in harsh environments for safety, functionality or improved noise immunity. This includes analog front-ends used in data acquisition modules for industrial measurement and control, as well as digital interfaces between processing nodes.

In the past, bandwidths of only up to a few megabits were sufficient for convertor interfaces or industrial backplanes, allowing isolation of protocols such as serial peripheral interface (SPI) or RS-485 using optocouplers. Digital isolators have improved the safety, performance and reliability of such isolated interfaces, as well as offering integrated isolation and I/O. However, trends such as Industry 4.0 and the Internet of Things (IoT) demand far more ubiquitous measurement and control, with greater speed and precision, resulting in greater demands for increased bandwidth.

The need for galvanic isolation also proliferates as these increased digital interactions with the physical domain demand protection from motor and power systems, human operators and electrostatic discharge, as well as external factors like surges due to lightning strikes. Precision measurements can also need isolation from noise sources such as more localised and miniature power circuits and high-speed digital processing.

Low Voltage Differential Signalling (LVDS) is a ubiquitous high-speed interface for higher-performance convertors and high bandwidth FPGA or ASIC I/O. The differential signalling offers high immunity to external electromagnetic interference (EMI) due to the mutual coupling between the inverting and non-inverting signals, which also correspondingly minimises any EMI created by the LVDS signalling. Adding isolation to LVDS interfaces provides a transparent solution that can be inserted into existing signal chains for high-speed and precision measurement and control applications.

What options exist today? 

Standard digital isolators remain a far faster, robust and more reliable solution than optocouplers for galvanic isolation of converter and processor interfaces. However, typical LVDS data rates to support high speed or precision convertors are in the hundreds of megabits, while the fastest standard digital isolators support up to 150 Mbps.

Figure 1. Value proposition of isolator implementations vs. isolator speed
 

To support isolating at higher bandwidths, system designers until now have turned to custom design-intensive solutions, such as deserialization or discrete solutions using transformers or capacitors. These add cost and design time, with deserialization potentially even requiring an extra simple FPGA just for that function, and transformers and capacitors requiring careful signal conditioning of LVDS signals and resulting in application and data-rate specific solutions requiring AC-balanced encoding.

A further solution is the use of fibre communication links, but this is better suited to multi-gigabit requirements due to the cost and increased complexity. The spectrum of options for isolating at high speed are shown in Figure 1, with the value proposition (depending on the ease of design and cost) plotted against the maximum speed of the implementation.

By contrast, as shown in Figure 2, Analog Devices has introduced a family of drop-in LVDS isolators, ADN4650/ADN4651/ADN4652, using iCoupler technology enhanced for operation up to 600 Mbps. In addition to TIA/EIA-644-A LVDS compliant I/O, the complete isolator signal chain is fully differential, realising a high-immunity and low emissions solution. Two isolated LVDS channels are provided, one transmit and one receive (ADN4651, or vice-versa for ADN4652) or two transmit or receive (ADN4650). The internal high-speed circuits operate at 2.5 V, which may not be present in industrial systems as a power rail, so internal low drop-out regulators (LDOs) are provided (as shown in Figure 3) to allow a single wide-body SOIC solution even when powering from 3.3 V supplies.

 

Figure 2. ADN4651 600 Mbps LVDS isolator block diagram

Continue reading the next page on Embedded's sister site, EDN: "Why isolate LVDS?."

 

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