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Reinventing JTAG for SoC debugging
Want a headstart on implementing a new JTAG debug interface into your design? Here's the lowdown on the soon-to-be IEEE 1149.7 standard.



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IEEE 1149.7
Currently, the IEEE 1149.7 standard is headed for ratification in 2009. The IEEE working group that developed the new standard collaborated with and built upon the work of two other standards bodies: the Mobile Industry Processor Interface (MIPI) group and the NEXUS (IEEE ISTO 5001) Consortium.

The standard's capabilities are conveniently structured into six classes with each class building on the capabilities developed in the previous classes.

The first four classes (Class T0 though T3) are essentially extensions to IEEE 1149.1. The second group (Class T4 and T5) implements and uses advanced two-pin operation. By employing this step-wise development model, the working group made it easier to grasp the implications of the new standard and provide designers with the ability to implement the necessary capability for their devices.

Class T0
Class T0 ensures compliance with the industry's current test infrastructure based on IEEE 1149.1. In class T0, after a test-logic-reset, all IEEE 1149.7 multi-tap devices must conform to the mandatory IEEE 1149.1 instruction behavior and implement a one-bit DR-scan for the bypass instruction.

Class T1
Class T1 defines the control system upon which the advanced capabilities of the subsequent classes are based.

In brief, the innovative control system employs IEEE 1149.1-compatible TAP state sequences and shift-state watching to create a control system as the zero-bit DR Scans (ZBSs) are employed to set the state of an IEEE 1149.7-compliant chip while leaving IEEE 1149.1-compliant chips completely unaffected.

ZBS state sequences are rarely, if ever, used with the BYPASS and IDCODE instructions in IEEE 1149.1 systems and perform no real function (see Figure 2). This is because the ZBS with these instructions is benign and does not materially change the state of the test logic.

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The yellow line in Figure 2 traces the path of a ZBS state sequence. The cartoon figure on the left of the diagram represents the control systems as it "watches" and counts the number of ZBSs the design engineer has initiated.

The ZBS begins at the Select-DR-Scan state through exit and proceeds to an Update-DR TAP controller state without changing anything in the TAP controller. As far as the IEEE 1149.1 standard is concerned, nothing of note has transpired.

However, logic represented by the cartoon face in Figure 2 keeps counting the number of times ZBS state sequences are initiated. When the ZBS sequence is broken by moving from the Capture-DR state to the Shift-DR state, the logic locks the ZBS count.

Locking the ZBS count activates a control level that is equal to the ZBS count (1 through 7). Control level two is used to create commands for the IEEE 1149.7 system. Control level functionality is shown in Table 1.

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A control level is exited when certain events occur. These events are the Select-IR-Scan controller state, the Test-Logic-Reset state, and certain controller commands and events that are meant to synchronize the operation of Class T4 and T5 controllers.

Class T1 is also helpful for controlling power. IEEE 1149.7 defines four power-down modes designed for use cases such as board testing, chip testing, and applications debugging. Defined power-down modes for the debug logic aids in reducing system power as well as provides a standard way for tools vendors to work with powered-down devices.

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