MPSoC Performance Analysis with Virtual Prototype Platforms

November 11, 2012

Bernard Cole-November 11, 2012

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In “MPSOC performance analysis with virtual prototyping platforms,” David Castells-Rufas, Jaume Joven, Sergi Risueño, Eduard Fernandez, and Jordi Carrabina of the Autonomous University in Bellaterra, Spain with co-authors Thomas William and Hartmut Mix show how performance analysis methods used successfully in high performance computing can adapted to the embedded domain using Virtual Prototypes based on Instruction Set Simulators.

They use this methodology to produce trace files by transparent Instrumentation based on instruction set simulation (ISS) that can be used for post-mortem performance Analysis. This use of ISS adds no overhead for trace generation and it solves the problem of trace storage.

They show how performance analysis of the virtual prototype is valuable way to optimize a parallel embedded test application, allowing an acceptable speedup factor on 4 processors to be obtained

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