Speedy bus mastering with PCI ExpressClick here to see all content
PCI Express (PCIe) is the fastest interface available to facilitate PC/FPGA communications. FPGA vendors have offered PCIe cores to harness this power for some time, but the cores are too rudimentary in nature to be of immediate use.
For example, while there have been recent enhancements, the Xilinx and Altera cores provide a split transmit (TX)/receive (RX) interface to the PCIe bus. However, the user must still encode or decode data to form packets while obeying the many rules of the PCIe specification for addressing, packet size, etc.
Once packets have been created, there are still several design hurdles and a great deal of code that must be written in order to turn these primitive interfaces into a useful core, user friendly bus access model for the hardware designer.
This paper discusses difficulties and insights related to the implementation of the PCIe protocol on the PC platform in the form of the Speedy PCIe core and offers it as a solution or starting point for future research.
The Speedy PCIe core delivers a general purpose solution that solves the problems of high speed Direct Memory Access (DMA) while offering an interface that is generic and adaptable for a large number of applications. The complete solution consists of a Windows 32/64-bit driver, FPGA Verilog and a C++ test application.
To read this article in full download the paper from the Microsoft resech on line technical paper archives.