Design Con 2015

Xilinx’s Virtex-7 2000T FPGAs

November 14, 2011

JackGanssle-November 14, 2011

In the “Holy Crap What’s Next?” department, Xilinx recently announced a new FPGA. Yawn, right? Well, this device is pretty astonishing.

Comprising 6.8 billion transistors, it offers 1,955,000 logic cells, which is equivalent to maybe 20m gates. There’s 46,512 Kb of Block RAM on-board. Tons of I/O is included, like 36 serial transceivers each capable of running at 12.5Gb/second.

Amazing fact number one: this high-end variant of Xilinx’s 28nm Virtex-7 family includes 2,160 DSP slices, each of which looks like this:

(From http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf)

Figure on 1,590 GMAC/sec of processing in these slices. This puppy is a supercomputer on a chip.

My friend Steve Leibson cites a demo of this part running 3600 nanoBlaze processors, for 180,000 MIPS at 20 watts. Wow!

The back story is one of power reduction. Every time a signal goes between chips speed degrades and the I/O requires a hefty driver. Xilinx used a high-k metal gate technology to reduce leakage, which is hardly novel. But then we come to amazing fact number two: the part is actually four chips mounted on a passive silicon “interposer,” which has four layers of metallization to interconnect the parts. The interposer removes the need for high-power I/O between parts while enhancing interchip communications speeds. The company claims a 5x speedup and 40% reduction in static power consumption.

The interposer is built with 65 nm geometry, and enables 10,000 connections between the four “Super Logic Regions” (SLRs). Things are arranged like this:

From http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

Note that all four SLRs are on top of a single interposer, and the whole affair rides on the package itself.

And what a package: 1925 solder balls, of which 1200 are user I/O, all in a 45 x 45 mm footprint.

Power (excluding I/O) is about a volt, pretty typical for this kind of technology. The part has a 40 watt max rating, so figure on a heck of a power supply. And 56 decoupling capacitors are recommended.

Everything about this part boggles the mind, including the configuration RAM that contains the user’s “design” of the FPGA… which can require up to 450 million bits.

They prefer not to quote a price to me, but I suspect it’s on par with a new Toyota.

Jack G. Ganssle is a lecturer and consultant on embedded development issues. He conducts seminars on embedded systems and helps companies with their embedded challenges. Contact him at jack@ganssle.com. His website is www.ganssle.com.

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