A crash course in multicore at ARM TechCon 2013Over the past few years, processor architectures on mobile and embedded consumer devices - most of them ARM-based - have not only increased in clock speed, but also made the step to multicore.
With the introduction of dual core processors for mobile devices in 2010 and quad core processors more recently, the available raw compute power increased significantly and with it, additional challenges, which have been covered well by Julio Diez Ruiz in “Overcoming the embedded CPU performance wall.”
Driven by the insatiable imaging and visual interface demands of consumer mobile and embedded users has led to the introduction of specialized graphics processor units. This has pushed developers to shift from relatively simple SMP configurations to the complexities of asymmetric heterogeneous architectures nd all the attendant hardware and software issues that raises.
At the 2013 ARM Technical Conference in two weeks, ARM developers who register to attend will have an array of resources available to them, including a special track of classes titled “Marrying software and hardware in multicore design,” which explores the interaction between hardware design and software structure as well as the techniques for ensuring an optimal working relationship between the two. Topics include big.LITTLE processing, dual core software partitioning, heterogeneous graphics processing, multi-core debugging and software optimization.
In addition, scattered throughout the three days of classes are about a dozen other multicore programming classes of which my Editor’s Top Picks are:
“Can Existing Embedded Applications Benefit from Multicore Technology? (ATC-103 ), where Niall Cooling of Feabhas Ltd. ( an Embedded.com contributor ) looks at this question from a software developer's perspective, assessing the claims code examples he says seem to demonstrate the (same) massive performance improvements when using, say, 16 or 128 cores. But is this valid in more traditional embedded multicore designs?
“Writing Reliable Multicore Code ( ATC-121),” where Greg Davis (another Embedded.com contributor) looks at the top sources of runtime errors in multicore systems and how to avoid them with reliable code.
“Advancements for Simplifying Multicore SoC-based Product Development and Debugging ( SS-840) ),” in which Mike Ahrens demonstrates how presentation and accompanying demonstration will show how multicore-ready operating systems, IDEs and hardware probes can deliver advanced, intuitive, easy-to-use embedded software debug capabilities. http://schedule.armtechcon.com/session-id/129
For more insight into such issues (a topic of ongoing interest at Embedded.com, check out our Multicore Archive of some of the several hundred multicore design articles published on the site. Also, this week’s Tech Focus Newsletter on “Learning new multicore development tricks,” has a number of recent design how-to tutorials, journal articles, white papers, and webinars on such topics as OpenMP/MCAPI synergisms, multicore best practices, decision-tree approaches to selecting multicore software, and multiOSes for multicores.
Some Embedded.com design articles which run counter to mainstream C programming approaches to multicore include:
In addition to some recently published journal articles and conference presentations that I’ve included in this week’s ,Tech Focus Newsletter here are my Editor’s Top Picks of some other content you should be interested in:
Be sure to register to attend the ARM Techcon in two weeks and catch up on the latest in multicore hardware and software design techniques. Maybe I’ll see you there!!!
Embedded.com Site Editor Bernard Cole is also editor of the twice-a-week Embedded.com newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to email@example.com, or call 928-525-9087.