Tales of embedded System-on-Chip design
There are two reasons I “enjoy” technical conferences such as this week’s 2014 DesignCon for self-described “chipheads.”
First, it gives me a chance to get an update on the variety of new tools available to embedded systems developers for easing the chore of system-on-chip designs and the many packaging and board problems that go along with it. But second and mfmore importantly it gives me a chance to read about or attend classes and presentations by developers who actually use these tools in their designs.
The presentations, classes and show floor booth demonstrations of the new tools and methodologies are all highly instructive. But it is the hands-on personal experience classes I keep watch for concerning the real capabilities and limitations of the new tools. More than that, it gives me a chance to see how engineers think and solve problems.
For attendees who register to attend the 2014 DesignCon starting this Tuesday in Santa Clara, Ca. there will certainly be many companies on the show floor demonstrating their new tools. In addition, with 150 papers and classes organized into 14 tracks I will certainly be watching for those about the new tools and methods the tools need to solve particularly troublesome SoC hardware problems.
But the papers and classes I will be really looking for are the ones that provide me with that personal “how I did it” point of view. Right now, the ones at the top of my Must-see List include:
Improving Crosstalk and Voltage Noise Immunity of On-Chip Busses
Modeling & Mitigating Power Supply Noise in Quad-Core CPU SoC & GPU Chipsets
Analyzing Impact of On-Chip Supply Noise Induced Jitter
Analysis of Digital IC Design: Methodology, Problems and Solutions
SoC Power Integrity from Early Estimation to Design Signoff
I would like to hear about your favorite and most useful classes at the show. For more hands-on embedded SoC design stories be sure to read this week’s Tech Focus newsletter with some of the most recent submissions to Embedded.com on this topic. From these and other such articles and blogs on this topic my Editor’s Top Picks are:
Using co-design to optimize system interconnect paths
A method to improve signal quality by optimizing components' interconnect paths on a printed circuit board.
Using SystemC to build a system-on-chip platform
How designers used the SystemC hardware design language to do performance modeling when creating both the company's OMAP-2 platform and the devices based on it.
Alternatives to ISS for hardware/software design exploration
While Instruction Set Simulation is good for early software debugging, it is not the best way to experiment with new architecture options such as a new bus topology, different memory hierarchy, or processor clock speed sizing.
Breathing life into hardware and software codesign
How hardware/software codesign evolved, what went wrong in early attempts, and how the use of transaction-level modeling has led to its revival and use.
I am always interested in seeing such hands-on personal experience kinds of articles and blogs for publication on Embedded.com, not only about SoC and board design and debug, but on the software side as well on such topics as compiler trade offs, ring buffer basics, and memory allocation.
And as recent articles and blogs on Embedded.com on virtual prototyping and hardware-software codesign illustrate, a number of tools and techniques for tighter linkage of hardware and software co-design and debug are becoming available. Given the important role software has taken on in most SoC designs, as you use these tools and gain more experience with them, I hope to hear from both hardware and software developers about your experiences - good or bad - and how you think things could be improved.Embedded.com Site Editor Bernard Cole is also editor of the twice-a-week Embedded.com newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to firstname.lastname@example.org, or call 928-525-9087.