Are we all in sync?The clock trees used in today's synchronous designs (be they implemented in ASIC, Structured ASIC, or FPGA fabric) consume a huge amount of power and resources. Furthermore, synchronous implementations are inherently limited as to the maximum frequency they can achieve by the worst-case (guard-banded) delays through any particular pipeline stage.
For this reason, I've long been interested in the concept of asynchronous systems. There are, of course, a number of disparate techniques that can be used to implement an asynchronous design. One I quite like is to realize the design as a large number of small blocks of logic, each of which accepts an "I've got something for you" flag from the previous (upstream) stage and generates an "I'm ready do do something" flag for use by the previous stage. Similarly, each stage generates an "Ive got something for you" flag for use by the following (downstream) stage and accepts an "I'm ready do do something" flag from that downstream stage.
In addition to the fact that we don't have to implement a clock tree, there are a number of advantages to this approach. For example, the design will always run at its maximum possible speed, and will adapt on the fly to different environmental conditions (temperature, voltage, etc.). Furthermore, any portions of the design that aren't actually doing something at any particular time will automatically not do anything at all (unlike synchronous designs in which we have to explicitly gate things off).
So I was very interested to read a recent EE Times News Item discussing how asynchronous logic design is becoming one of the better-kept secrets in the chip design community. This started me to wondering if any FPGA vendors are contemplating releasing special devices and tools to take advantage of this form of design. Hmmm, I'll have to ask around...