SoC low-power verification requires a full-chip solution

Brian Bailey

April 13, 2012

Brian Bailey

Thomas L. Anderson Vice President of Marketing Breker Verification Systems, Inc.

Not too long ago, low-power design was an esoteric discipline practiced mostly by makers of digital watches and calculators. In the last 20 years, a steady series of new products that run on batteries for much of their lives has brought the need for power conservation to the forefront of the electronics business. Cell phones, smart phones, tablets, and other consumer devices have sophisticated, power-hungry processors and wireless links. Further, “green” laws and industry initiatives have mandated lower power even for “big iron” servers, switches, and telephony equipment.

At the heart of all these products are system-on-chip (SoC) designs combining one or more embedded processors with a variety of functional units, all interconnected by some type of bus or fabric. There is a wide range of techniques used to reduce the power consumed by these SoCs, including innovative transistor and cell designs, substrate biasing, and varying voltages. These have no significant effect on verification of the system model or the RTL design. However, the technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). Shutting off functional units not currently needed clearly saves both leakage current and dynamic power.

While simple in concept, PSO has many tricky aspects in implementation that must be carefully verified. For example, it may be necessary to save some of the state (registers or memory) in a powered-down unit. When a unit is powered down, its outputs will not be valid and so must be isolated from other units. Powering a unit up or down requires a specific set of steps in the right order. Also, only specific combinations of units may be powered down or up at a time. In fact, it’s possible that powering up the entire chip at once is prohibited due to excessive current requirements.

All of these implementation details must be verified using the RTL design, and preferably on the system-level model first. The implications of PSO reach all the way up to the system architect, who needs to determine which units can be safely powered down, and under what circumstances. There is a tendency for both the system and RTL verification teams to focus mostly on the Power Control Module (PCM), a state machine that issues the signals for the power-up and power-down sequences. These signals control isolation of powered-down units, saving and restoration of any retained state within the powered-down units, and turning off and on power to the units.

The PCM’s proper sequencing of the isolation, retention, and power signals is very important. Since the PCM is a finite state machine, its legal transitions and required outputs can be captured in the form of assertions and verified by formal analysis. [1] In many cases this verification is exhaustive, at least relative to the set of assertions provided. If the PCM is verified using simulation rather than formal analysis, it is essential that all its paths are exercised. Applying coverage to the states and transitions of the PCM is an excellent way to gauge the thoroughness of the verification.

Although fully exercising the PCM is a critical part of PSO verification, it is by no means sufficient. It is also necessary to simulate the effects of the powered-up and powered-down units together, in all legal combinations if possible. There are many common design errors relating to PSO that can be checked in simulation, including:

• A powered-down unit may be unable to power up again
• A unit may power down before its retained state has been saved
• A powered-down unit may power up without its retained state intact
• A unit may power up and start running before its state has been restored
• A powered-down unit or another unit may rely on state that was not retained
• Another unit may rely on signals that have been isolated from a powered-down unit

In theory, many of these problems could also be found by formal analysis, but in practice the combination of multiple functional units is too large for formal tools to handle. Instead, verification engineers develop sophisticated testbenches that use constrained-random techniques to run various combinations of powering up and down the functional units. Modern simulators model the effects of powering down by forcing unretained state to “unknown” and isolated signals to appropriate values. The Universal Verification Methodology (UVM) standard has been extended in order to perform this type of multi-unit PSO verification. [2]

Of course the full range of functional units and PSO behavior can only be verified at the full-chip level. It is increasingly clear that the UVM, for all its virtues, is not being widely used for complete SoCs. There are three main reasons for this: the difficulty of developing a constrained-random testbench for all the complex interfaces on a large SoC, slow simulation speed at the full-chip level, and the lack of any interaction or coordination between the testbench and the SoC’s embedded processors.

This last issue is a major one for verifying low-power designs at the full-chip level, especially for those using PSO. In SoC real-world operation, the PCM is primarily controlled by software running on the embedded processors. PowerWise and similar initiatives recognize that intelligent power-control decisions can be made by system-level software. [3] Trying to replicate this functionality using only an external testbench is a significant challenge. A much better approach is to use the embedded processors in simulation to exercise all the PSO modes of the SoC.

Running the production code on the embedded processors in simulation is usually not an option; it can take a very long time just to boot the operating system. This is feasible on a simulation accelerator, but production code is not very efficient at exercising corner cases or all possible PSO combinations. Hand-written C tests for the embedded processors can be more focused on low-power verification, but they are time-consuming and difficult to write. The ideal solution is automatically generated self-verifying C test cases running on the embedded processors in simulation and coordinated with a simple testbench.

Tools such as TrekSoC from Breker Verification Systems provide a solution for many aspects of full-SoC verification, including PSO functionality in low-power design. As with other aspects of system-level behavior, the designer or verification engineer can capture the low-power operation in an intuitive scenario model. These tools construct a graph-based representation of the SoC’s operation and automatically generate embedded C test cases as well as an efficient connection to the testbench. Results are presented in a graphical format that shows achieved coverage and flags unreachable paths. [4] They can be used to verify individual functional units, including the PCM, as well.

Verification of proper low-power operation in a large, complex SoC is far from a simple task. Focusing only on the PCM, building a full-SoC testbench, or relying on unoptimized software is inefficient and frequently ineffective. The best way to verify low-power functionality, especially for PSO-based designs, is to combine the power of scenario models, self-verifying test cases, and graphical results. This powerful solution is applicable to the challenge of SoC low-power verification.

References:
 [1]    “Formal Validation of Low-Power Designs” by Chris Komar, Tom Anderson and Jerry Church, CDNLive! Silicon Valley 2007 Proceedings, September 2007 http://www.cadence.com/rl/Resources/conference_papers/2.6Paper.pdf
[2]    Advanced Verification Topics, Cadence Design Systems, Inc., 2011 http://www.cadence.com/products/fv/Pages/advanced_verification.aspx
[3]    “About PowerWise® Interface (PWI)” http://www.national.com/pwi/index.html
[4]    “The Truth about SoC Verification” by Adnan Hamid, Assembling the Future, February 2012 http://www.gabeoneda.com/newsletter/pdf/2012/02

About the Author:
Thomas L. Anderson is vice president of Marketing for Breker Verification Systems. His previous positions include Product Management group director of Advanced Verification Systems at Cadence, director of Technical Marketing in the Verification Group at Synopsys, vice president of Applications Engineering at 0-In Design Automation, and vice president of Engineering at Virtual Chips. Anderson has presented more than 100 conference talks and published more than 150 papers and technical articles on such topics as advanced verification, formal analysis, SystemVerilog, and design reuse. He holds an Master of Science degree in Electrical Engineering and Computer Science from MIT and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

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