What will change on the road to 3D ICs?
3D-IC represents different benefits for different applications. It can be both a performance enhancer and a power reducer due to shorter, lower capacitance interconnect lines, for example when used to stack memory on logic. It can provide a smaller overall footprint for mobile apps like cell phones, and it can improve yield when multiple smaller die can be assembled in lieu of a large SoC during early process maturity. It also allows analog and digital IP to hit performance and integration targets without forcing implementation in a single process. Depending on the application targeted, the jury is still out about relative costs and reliability, but there expectations for improvement in the long run in these areas as well.
For the next 2-3 years, companies are primarily pursuing 2.5D approaches using silicon interposers (SI) for denser packaging, higher bandwidth and integration of memory, sensors and mixed signal designs based on existing partitioning schemes. SIs have the advantage of simplicity and easier thermal management challenges. The tooling requirements here are incremental: verification tools have been extended to handle new design rules, inter-die alignment and cross-die connectivity checking. Testing tools have new features to allow test access to die that are not physically accessible by test equipment after stacking and packaging. New extraction models are being developed to provide more accurate TSV modeling, and place and route tools have some additional package floorplanning, placement and pin-out capabilities.
When we begin to discuss full 3D, where through silicon vias (TSV) are used to connect two or more disparate processed dies with active circuit area, we expect the first applications to be memory on logic and sensor on logic. For memory on logic in particular, the wide I/O standard, driven through a TSV, has very attractive characteristics for power management. Here the tool extensions developed for interposer based designs will also be leveraged, with memory BIST taking on an increased importance for both validation and repair of the stacked memory.
Though often talked about as a scaling alternative, we would expect few applications of homogeneous logic partitioned across multiple die in the medium term. The exception may be for cases where there is an architectural advantage for dataflow that moves in a vertical dimension. One potential may be for GPU. Here the fact that architecture will drive portioning will allow the use of current place and route technology with minor enhancements for physical implementation.
In the long term, getting to a full use of 3D stacking of homogeneous logic dies, perhaps in reaction to a final end to transistor scaling, will require more extensive changes to the design flow. This will include design and simulation techniques that enable TSVs in active circuit areas, integration of logical and physical design tools to permit system-level optimization across die, and improvements in thermal, power delivery, and package design and modeling tools.
Joseph Sawicki is vice president and general manager of Mentor Graphics Corp.'s Design-to-Silicon division.
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