The signal integrity challenges in nextgen embedded designs

Today's high-speed communications designs with all their associated signal integrity issues could be tomorrow's challenges in mainstream embedded and mobile designs, so it is wise to keep an eye on how hardware chipheads are dealing with such problems.

Innovative defense techniques for damping digital to RF crosstalk

Many mobile devices have multiple-input-multiple-output (MIMO) on-board antennas and present many challenges to signal integrity. Here is one approach to design that reduces noise significantly and makes comm links more immune to interference.

Addressing MIPI M-PHY connectivity challenges for more efficient testing

As the industry moves to adopt the MIPI Alliance’s M-PHY standard, designers are encountering some significant challenges related to oscilloscope measurements and, more specifically, probing.

Designing optimal wireless basestation MIMO antennae: Part 1 - Sorting out the confusion

In Part 1 of a two-part series, the authors delineate the various types of multiple input, multiple output (MIMO) antennae and provide some guidelines on how to make the right choices in a wireless base station design.

Simplify the design of the cellular base station digital predistortion subsystems

How to use a digital predistortion micromodule to build a fully integrated digital predistortion (DPD) reciver for use in cellular network base station designs.

ABCs of signal integrity for embedded developers – Part 1: Basic SI rules and methods

ABCs of signal integrity - Part 1 explores some of the challenges of designing for signal integrity and possible solutions.

Using clock generators/buffers to adapt your PCIe design to specific application needs

With the correct mix of PCIe clock generators and buffers, embedded systems developers can address the unique requirements of various applications.

How to enhance signal integrity in high density FPGA-based designs

The authors discuss the anomalies that can be introduced between the connecting wires on a high-density FPGA-based board and how to prevent them.

Building quality & signal integrity into PoP-based PCB design & assembly

Why designers of printed circuit boards for nextgen ICs need to be savvy about package-on-package technology.

Signal versus power integrity in high-speed embedded design

Analysis of both signal integrity and power integrity is vital to a successful high-speed digital design. Here's some perspective on why this is so and why in embedded designs the two need not be working a cross-purposes to one another.

Improve FPGA communications interface clock jitters with external PLLs

The problems faced in dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes and how external phase locked loops (PLLs) can be used to resolve them.

Doing jitter timing analysis in the presence of system crosstalk

Jitter has become a significant percentage of a signal's interval, making it increasingly important to fully understand its types and sources. Most high-speed serial designs now use multiple lanes. Thus, crosstalk is nearly unavoidable.

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