Bit-banging pulse density modulation
Single-pole low-pass filter
The simple RC filter is a single-pole low-pass filter. The Bode plot of the filter, along with the critical frequencies is shown in Figure 2.
Click on image to enlarge.
Figure 2: A single-pole RC filter for the pulse density modulator.
The critical parameters to note are the two frequencies FPDM and FFILT. These are the PDM half-density frequency and the low-pass filter cut-off frequency respectively.
The PDM half-density frequency is the equivalent to the frequency of the pulse density output at a 50%. This frequency is related to the sampling frequency FS as shown in Equation 1:
Equation 1: The relationship between the pulse density half-duty frequency and the sampling frequency.
Again, we need to bring back the cut-off frequency for the single-pole low-pass filter as we described in the last article. Equation 2 shows this inequality:
Equation 2: Inequality relation between low-pass cut-off frequency and the filter time constant
We also need to constrain the 1% voltage ripple between the low pass filter cut-off and the PDM half-density frequency. Equation 3 shows this relationship:
Equation 3: Relationship between the cut-off frequency and the PDM half-duty frequency.
Combining Equation 2 and Equation 3 will yield the inequality which relates the RC filter time constant to the PDM half-duty frequency. This is shown as Equation 4:
Equation 4: RC filter time constant relationship with the PDM half-duty frequency.
So, let us plug in some numbers here. If we use a sampling frequency of 10,240 Hertz, and plug this into Equation 1, we get Equation 5 for FPDM:
Equation 5: Calculation of the PDM half-duty frequency.
We can immediately see the much higher frequency of the half-density PDM as compared with the full-cycle PWM. This is a 128-fold improvement.
Substituting the result from Equation 5 into Equation 4 will yield the minimum RC time constant for our simple single-pole low-pass filter. This is shown in Equation 6. Clearly, this shows the 128-fold improvement in the RC time constant. This will also make the step response for the D/A output much quicker too.
Equation 6. PDM low-pass filter time constant.
Design and implementation
OK, now that you can see that the PDM controller is something you'd want, how do you implement it? You can go to the Internet and type in a Google search, or maybe go to Wikipedia. These two options will give one a pretty decent idea of how a PDM controller ought to work.
However, the articles and references are pretty sketchy when it comes to details.
The basic idea of how to generate a density of PDM pulses comes from the idea of the sigma-delta analog to digital converter. The idea is to keep an integrator, which integrates an error signal. We feed this error signal back and keep adjusting (adding or subtracting from the integrator), until we get a minimum error signal.
This idea is difficult to envision because we are talking about feedback here. Maybe it is better to represent this idea as some kind of pretty picture. Figure 3 shows the input (DAC VALUE), the output (pulses), the main control unit (error integrator, summing junction + comparator), and the DAC MAX level switch (DMAX switch).
Click on image to enlarge.
Figure 3: Pulse density modulator control block diagram.
The DMAX value is the number of total DAC states on the converter. This will be 256 for an 8-bit converter. The DMAX value for a 10-bit converter will be 1,024 states. One interesting side effect of the DMAX value is that we can now support DAC states that are not 2N as in a typical D-A converter.