The many routes to low-power design at ARM TechconAs editor of the Embedded.com web site and its twice-weekly newsletters, I would have to be deaf and blind not to be aware of the continuing intense interest by embedded systems developers in finding more and better ways to lower power consumption and improve the energy efficiency of their designs.
Some of the recent contributed design articles, product how-tos, blogs, white papers and webinars on these topics are included in this week’s Tech Focus newsletter on ”Low power & energy efficient designs.” In addition, some older, but still relevant blogs and articles on the site that are my Editor’s Top Picks include:
Choosing the right low power ARM processor for your embedded design
System level software centric power debugging using virtual prototypes
It’s all about tools - developing power-sensitive, low current MCU designs
Because ARM processors and MCU play a large part in any embedded developers professional life, the same all-consuming focus will be on display for registered attendees at the upcoming ARM Technical Conference, Oct. 29-31. There attendees will be able to take advantage of more than a dozen papers and classes on low power and energy efficient ARM design, of which my Must-Attend Recommendations are:
Drive Down System Power and Bandwidth with ARM Multimedia IP (ATC-124), in which ARM’s Alexis Mather provides a comprehensive review , of the various CPUs, GPUs, and video engines and ways to reduce memory bandwidth and system power.
The ABCs of Power Management for Cortex M (ATC-315) in which GE Transportation’s Mark Kraeling goes over the various power modes. Each mode requires a specific interface design, so that critical elements of the system aren't disabled unexpectedly. In addition, various power-level measurements are provided, giving insight into possible power savings.
Building the Highest-Efficiency, Lowest-Power, Lowest-Cost Cortex-A Processor-based Mobile Devices (ATC-223) in which ARM’s William Orme describes how to build an extremely efficient processing subsystem, based on the very latest, lowest-power ARM Cortex-A class processors, Mali graphics and video processors, and CoreLink PD-System IP. http://schedule.armtechcon.com/session-id/12
Maximizing Performance of ARM Cortex-A15 for Ultra-Power-Constrained Mobile (ATC104) in which Cadence’s Paddy Mamtora discusses the highly power-optimized implementation of a dual-core Cortex-A15 on a TSMC 28nm HPM process with ARM nine-track POP IP and Cadence's Encounter RTL-to-signoff flows. We describe the various challenges and choices involved as well as the power-management techniques used.
In addition to those included in this week's newsletter, some Embedded.com articles, conference presentations and professional journal articles which may help you prepare for an intense three days of intense education at ARM Techcon include:
Other power and energy management classes at ARM Techcon that you might want to check out include:
Power-Aware Thread Scheduling
Realizing High-performance and Power Efficient Implementations of ARM’s Cortex-A57
ARM based SoC’s Power, Performance and Area: More than just Three Numbers
A Power, Performance, and Cost Optimized Cortex-A12 in 28nm- SLP
Strategic Analog Power Management IP for Systems on a Chip
Low-Power Cellular-Connected IoT Devices
Reliable Ultralow-Power Wireless Sensing with SmartMesh IP
Be sure to register to attend ARM Techcon. Maybe we will see each other there and get a chance to indulge in the original - and still most effective - form of social networking: face-to-face conversation.
Embedded.com Site Editor Bernard Cole is also editor of the twice-a-week Embedded.com newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to email@example.com, or call 928-525-9087.