Design Con 2015

The role of PLLs in 21st century embedded design

February 23, 2014

Bernard Cole-February 23, 2014

For an integrated circuit building block that came into being at about the same time as the microprocessor in the late 1960s and early 1970s, the lowly phase-locked loop has not done too badly either.

I first came across the first IC-based PLLs while working at the California Institute of Technology as a staff writer, editor, and ghostwriter. While there I also audited as many classes in electronics as I could in which we had a chance to experiment with some of the new circuit designs emerging from "start-ups" like Intel, with its first microprocessors, and Signetics, which had just introduced its ground-breaking NE565 phase-locked loop IC.

The concept behind the PLL was - and still is - simple and elegant. At its core it is nothing more than a variable frequency oscillator and a phase detector. The first creates a periodic signal and the second compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched, bringing the output signal back toward the input signal for comparison by means of a feedback loop. Because keeping the input and output phase in sync means keeping the input and output frequencies the same, a PLL can also be used to track an input frequency or generate a frequency that is a multiple of the input frequency, among other things for computer clock synchronization, demodulation, and frequency synthesis.

But while I had fun with the others in the classes trying to see what new ways we could use the NE565 in various designs, most of my attention was distracted by the emergence of the first microprocessor, Intel's 4004, which we also got to play with.

By the time I left Caltech a few years later, both fundamental building blocks had proliferated. For a good understanding of the history of the PLL in all its technical detail, I recommend reading "Phase-locked loop design through the decades."

Now, just as microprocessors have become a fundamental building block in all electronics systems, so too with the PLL - with a vengeance. But where microprocessors are coalescing around a few basic architectural types, the types of PLLs continue to proliferate into several different variations including: analog or linear PLL (APLL), digital PLL (DPLL), software PLL (SPLL), and, just recently, neuronal PLLs (NPLLs), as well as combinations of all of these in a number of interesting hybrid designs (HPLLs?).

PLLs presently are as ubiquitous in electronics designs as microprocessors and microcontrollers, maybe even more so. Whether at the system, board, or system-on-chip level, for every MCU or MPU there are probably half a dozen companion PLL circuits in the same design to address such issues as clock generation and recovery, de-skewing, spread spectrum, clock distribution, jitter and noise reduction, and frequency synthesis.

Ashish Kumar and Sanjay Agarwal are the authors of "Phase-locked loops in an IC-based clock distribution system," a three part series featured in this week's Tech Focus newsletter on "The care and feeding of Phase-Locked Loops." It is their contention that the distributed nature of PLLs brings a new set of problems to the embedded designer: how to make all these local PLLs march in lock-step with the others, and avoid contributing to the problems the circuits were supposed to solve. Their exhaustive but clearly written analysis is well worth reading not once, but several times. In addition to their contribution, other articles on this topic on my Editor's Top Picks list are:

Dealing with PLL clock jitter in advanced processor designs
How to use an FPGA to test a PLL band calibration algorithm
Optimizing clock tree distribution in SoCs with multiple clock sinks

In addition, to get some idea of the range of designs in which PLLs play an important role, I recommend the following:

Extracting clock signals from high-speed communications
Keeping time on 40-100G networks with high-performance clocks
An introduction to Synchronized Ethernet

Embedded systems hardware designers continue to come up with new and interesting ways to use PLLs. A few of the interesting examples I have found in my searches on the web include:

Two gates and a microprocessor form digital PLL
Build a digital PLL with three ICs
PLL filter blocks undesired frequencies
Capacitance meter uses PLL for high accuracy

Because of their continuing importance in embedded designs, I expect that hardware developers will continue to find new ways to make PLLs “do tricks.” If you have an interesting design you have developed, give me a call or an email and we can work together on a blog or design article in which you can share your experiences with the rest of the embedded systems design community.

Embedded.com Site Editor Bernard Cole is also editor of the twice-a-week Embedded.com newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to bccole@acm.org, or call 928-525-9087.

See more articles and column like this one on Embedded.com. Sign up for subscriptions and newsletters. Copyright © 2014 UBM--All rights reserved.

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