Monolithic embedded RRAM presents challenges, opportunities
Smaller, faster, cheaper. Repeat. This has been the mantra of the semiconductor industry for more than 50 years, ever since Douglas Engelbart, a computer engineer, first introduced the elegant but radical idea of “scaling” to the electronics industry in 1960. Speaking at the first International Solid-State Circuits Conference, Engelbart’s idea was deceptively simple: as you make electronic circuitry smaller, components will get faster, less expensive and less power hungry.
The corollary to scale is integration. As individual transistors and other components get smaller, more of them can be combined – integrated – on a single chip. From discrete logic functions to microprocessors to microcontrollers to systems on chip, the industry has progressed to higher and higher degrees of integration as it has learned to make transistors and other components smaller and smaller.
But not all things have been able to shrink at the same rate. Most notably, memory technologies have not been able to scale as fast as other logic circuitry. This has resulted in a divergence between these two critical segments of the semiconductor industry, with different manufacturing processes for each that require separate manufacturing foundries on two distinct technology paths. And with memory and logic being manufactured on different process nodes, they cannot be integrated on the same chip.
Now engineers are looking up, literally, and moving into the third dimension as they seek to achieve even greater levels of integration. Moving from 2D planar topologies to 3D implementations offers many desirable benefits, including smaller overall footprint and shorter average interconnection length, along with associated improvements in cost, latency and energy consumption. But with logic and memory unable to reside on the same chip, engineers have been forced to consider a number of alternative methods for stacking individual chips and connecting them, including through silicon vias (TSVs) and silicon interposers, to achieve their integration goals. But this kind of stacking is also plagued by temperature, yield and other issues.
Enter nonvolatile resistive RAM (RRAM) technology. RRAM can be manufactured with the same CMOS process node in the same manufacturing foundry used today by logic circuitry. This manufacturing convergence, together with other unique features of RRAM technology, is making 3D monolithic integration of massive amounts of storage-class memory and logic circuitry possible for the first time. By eliminating expensive interposer and other chip-to-chip and stacked chip integration techniques and their limitations, RRAM technology enables system-on-chip architectures to benefit from the superior characteristics of embedded storage in the next generation computing platforms, creating new markets and new opportunities for monolithic embedded storage.
Since its introduction in 1987 by Dr. Fujio Masuoka from Toshiba, NAND flash technology has achieved the largest share of the nonvolatile memory (NVM) market. Today, NAND flash is the preferred mass storage media across a broad range of consumer applications, including tablets, smart phones, media players, cameras and video recorders, as well as in solid state drives (SSD) to boost the performance of computers, from slim laptops to massive enterprise storage systems.
But this 30-year old technology has recently begun showing its age. It is now widely accepted that scaling NAND flash below 25nm has significantly degraded performance and reliability. For example, scaling from 72nm to 16nm has shown an increase of the raw bit error rate (BER) from 1e-7 to 1e-2 and a decrease of cycling from 10,000 cycles to below 3,000 cycles. This, in turn, demands increased overhead and computational power from the NAND controller logic and the host system to compensate.
NAND flash is hitting this technology wall just as emerging storage applications are demand higher reliability and endurance. Current 2D planar NAND flash technology has reached a limit that will not be able to serve these applications.
This widening gap between application requirements and flash technology has spurred industry professionals to look into new solutions, including various 3D approaches, to resolve these issues while boosting density. While these efforts are commendable and may achieve some near-term success, NAND flash will always remain a separate component of any system, and designers will still need to contend with all that implies, from bandwidth and latency limitations to costs and burdensome power requirements and more.
The industry needs a fresh approach that not only addresses the scaling and reliability issues confronting NAND flash, but also the larger issues of achieving higher levels of integration between logic and memory. And this will be possible only when these two manufacturing process nodes converge again.
RRAM is widely hailed as the most promising technology in the race to develop new, more scalable, high-capacity, high-performance and reliable storage solutions. RRAM technology is based on a simple two-terminal device structure integrated in back-end-of-line (BEOL) process. RRAM cells typically employ a switching material sandwiched between two metallic electrodes that can exhibit different resistance characteristics when a voltage is applied across it. Significant performance differences can be achieved depending on the switching materials and memory cell organization chosen. When the RRAM technology uses CMOS-friendly materials and standard CMOS manufacturing processes, multiple layers of cross-point RRAM arrays can be integrated on top of CMOS logic wafers to build SoCs and other chips with large amounts of 3D monolithic embedded RRAM storage.
Regardless of the material specifics, developers of RRAM technology all face several common challenges: overcoming temperature sensitivity, integrating with standard CMOS technology and manufacturing processes and limiting the effects of sneak path currents, which would otherwise disrupt the stability of the data contained in each memory cell.