QuickLogic intros hybrid serdes line
Further blurring the lines between programmable and application-specific logic, QuickLogic Corp. is unveiling a family of hybrid devices that embed bus LVDS serializer/deserializer (serdes) blocks with an FPGA.
The QuickSD family of Embedded Standard Products (ESPs) integrates up to eight 1-Gbit/s serial data channels with embedded serdes, clock and data recovery, memory, DSP, and a large customizable logic array to deliver data rates of up to 8 Gbits/s, according to company executives. The three-member family lays the foundation for QuickLogic's new QuickCOM ESP series aimed at high-speed communications.
As rising bandwidth demands push the limits of parallel data buses, system architectures are moving toward serial structures-primarily switched topologies-to move bits at higher speeds, whether from chip to chip, board to board, or box to box, said Kevin Yee, director of applications and product planning at QuickLogic, Sunnyvale, Calif.
"Before, it was, 'How fast can I get my processor?' Now it's, 'How quickly can I get data from one chip to the next?' " Yee said.
By pulling in elements from each of its ESP families and soft-IP-function cores developed for its general-purpose FPGAs, QuickLogic claims to offer a complete building block for telecom and datacom switching systems, with enough flexibility built in to target other areas, such as high-speed backplanes, optical networks, and video and imaging processing and transmission.
The QuickSD family, along with the company's recently announced QuickFC family of customizable Fibre Channel devices, are "part of QuickLogic's initiative to directly address the industry's move to serial-bus architectures," said Tom Hart, president and chief executive of QuickLogic.
In its quest to distance its ESPs from the general-purpose PLDs touted by the dominant suppliers, QuickLogic is trekking into the territory of a different breed of giant. The company will position itself alongside LVDS market leaders such as Cypress Semiconductor, National Semiconductor, and Texas Instruments, as well as newcomers Pericom Semiconductor, PMC-Sierra, and Vitesse, according to Yee.
QuickLogic's serdes block handles all transceiver and PLL functions for each data channel, as well as the conversion from serial to parallel or parallel to serial-more than any standard part available today, Yee said. In addition, QuickLogic's embedded RAM provides the asynchronous FIFO function that would otherwise require a separate chip per channel.
"To do a 10-channel system today with standard parts would require 20 components," Yee said. "By integrating these functions into one, we reduce routing problems, component count, and board space, which adds up to 40% lower power [consumption] per channel."
At the same time, the device delivers the gigabit speeds traditional PLDs have trouble reaching, while preserving flexibility and fast design turnaround.
The hybrid approach was pioneered by Lucent Technologies Inc.'s Microelectronics Group, which has used its Field Programmable System Chips as an intermediate solution when its standard products, FPGAs, or ASICs don't fill the need.
"Uncertainty of standards means telcos have to support different kinds of services," said Samir Samhouri, general manager of Netcom products at Lucent's microelectronics unit in Allentown, Pa. "The difficult pieces that can't be put in an FPGA, we put in ASIC blocks [next to an FPGA block], and provide the additional IP to make the solution complete."
While QuickLogic rejects comparisons to Lucent, by embedding specialized high-speed communications functions, such as LVDS serdes links, the company is in fact entering a domain that, up to now, has been Lucent's alone.
Samhouri said Lucent's serdes macro is designed to support 1.25-, 2.5-, and 3.125-Gbit/s rates, and from two to eight channels.
QuickLogic's serdes family, however, is built to address a wider base of applications than Lucent's parts, according to Yee. The QuickSD family includes three devices with up to 658,000 programmable system gates.
Initially sampling is the QL82SD, which features eight 1-Gbit/s serdes data channels and two bus LVDS clock channels. The chip has 536,712 programmable system gates, including 2,016 logic cells, 18 3-bit multiply and accumulate blocks, and 83 Kbits of dual-port RAM. The larger QL84SD has the same number of channels, but more logic and memory resources for more complex interfaces. Rounding out the family, the QL81SD has six serdes and two bus LVDS channels, and fewer logic and memory cells.
Prices start at $25 in 10,000-unit volumes.
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