Intel ponders trigate transistor at 30 nm
Santa Clara, Calif. - Intel Corp. has taken the wraps off a new transistor structure that's thought to provide a pathway to the 30-nanometer line widths in future semiconductors. The vertical trigate transistor structure, unveiled last week at the International VLSI Symposium in Kyoto, Japan, provides high drive current, low leakage current and a minimum of manufacturing difficulties, Intel said.
The trigate transistor is one of the "pathfinder" technologies Intel is considering for fabrication processes expected to come online in 2007, said Ken David, co-director for components research at Intel's logic technology development and manufacturing group. The transistor structure is almost the same as that of the FinFET device Intel described earlier, at the International Solid-State Circuits Conference, as suitable for 60-nm production. Unlike planar transistors used with current-generation CMOS, which provide a flat, tablelike path between source and drain terminals, the FinFET gives that silicon slab a vertical orientation, like the fin of a shark.
But manufacturing will be an issue with the FinFET technology, David said. With its vertical orientation, the width of the silicon slab-the fin-must be less than two-thirds the thickness of the gate, which is also vertical. Thus, when attempting to manufacture devices at the 45-nm node, it will be necessary to etch fins that are 35 nm thick, or almost a full process generation ahead.
The relative dimensions of the gate, source and drain are far less critical with the vertical trigate structure, wherein the transistor switches function in a depletion mode and multiple gates are used to turn transistors off. On top of this, the turn-on/turn-off characteristics of the device offer improvements over today's advanced CMOS, Intel said. According to the VLSI Symposium presentation, these new devices show a high drive current of 1.23 milliamps per micron, and scant leakage current of 40 nA in the off state.
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