Winning core silicon game takes more than luck
Paper, rock or scissors? Picking the right one, plus a lot of luck, makes the difference between winning and losing the timeless game of chance.
Designers of electronic products face their own three-way choice every time they begin work on a new project: whether to use an application-specific integrated circuit (ASIC), a programmable-logic device (PLD) or an application-specific standard product (ASSP) as the core silicon at the heart of their system.
With the core silicon accounting for much of the value of an electronic product, making the right choice among the three options separates victory from defeat, just as in the game of paper, rock, scissors. However, unlike the game, designers don't have to rely on the vagaries of chance when picking their chip. By understanding the respective advantages and disadvantages of each approach, and by matching those attributes to the specific characteristics of the product, a designer can win every round.
This article will examine the three approaches to core silicon and discuss the parameters designers need to consider when choosing which type is right for their product.
Sizing up core silicon
The three contenders to fill the core silicon role are competing for a rich prize indeed. The total market for ASICs, PLDs and ASSPs exceeded $67 billion in 2003 alone and will grow to around $110 billion by 2008, iSuppli Corp. predicts. The estimates and forecasts for these products include revenue from all ASSPs, ASICs and PLDs, even though some of these parts are classified by their suppliers as DSPs or analog components in compliance with World Semiconductor Trade Statistics definitions.
For suppliers, a single design win can be worth hundreds of millions of dollars in lifetime revenue. For users, the choice among PLDs, ASICs and ASSPs for a system's core silicon has profound implications that ripple far beyond that system's technical specifications, to include the distribution channel, supply chain management, type of customers served and virtually every other aspect of what defines a product.
Catching the wave
In 1991, Tsugio Makimoto of Sony Corp. devised a model to explain some of the cyclical nature of the semiconductor industry. According to this model, known as Makimoto's Wave, there is a 10-year cycle during which electronic products migrate from standard parts to custom devices before reversing the process.
The mid-1990s were characterized by an explosion in new application areas, ranging from high-end communications equipment to novel consumer products. During those years, there was a relatively inexpensive path to developing the custom silicon needed to power such systems: the ASIC.
The number of new ASIC designs, both gate array and the newer cell-based architectures, reached dizzying heights in that decade, likely totaling more than 10,000 each year. Each top-tier ASIC provider could count on 400 to 500 design wins annually, amounting to almost two new designs for every working day of the year.
Since then, Makimoto's Wave has pushed the market to the middle of the standard-product phase. This is confirmed by industry results that show ASSPs outselling ASICs by roughly two to one. If the past predicts the future, then ASICs should recapture the lead from ASSPs late in this decade.
But trends in design starts tell a different story one that shows the shift from standard to custom products will occur much further in the future than the cycle would foretell. In fact, this transition may never happen at all, iSuppli believes.
Back to the future
In the ASIC world, history does predict the future. In this case, however, history is recounted by the number of design starts, a metric that serves as an extraordinarily accurate leading indicator of the market's direction.
Since the heady days of 10 years ago, the number of ASIC design starts has been on a monotonous decline. There are multiple reasons for this falloff. Some of them are favorable, such as the increasing levels of system integration, wherein a new design might reuse multiple chips from a previous-generation product. For ASIC suppliers, this generates greater lifetime revenue from a single design, compensating somewhat for the overall reduction in the number of wins.
Given the vastly improved capabilities of chips what occupied the entire core of a 7 x 7-mm die in 1997 now takes just a few square millimeters this functional aggregation has been inevitable as users benefit from higher performance and a lower bill of materials.
However, some of the factors depressing ASIC design starts are not so benign. And iSuppli believes these causes account for the majority of the drop.
"Your strength will become your weakness," said the famous Chinese military leader and strategist Sun Tzu. The general's maxim has turned out to be correct once again, this time in the ASIC industry.
In the mid-1990s, cell-based ASICs offered levels of integration, complexity and performance previously unattainable, except by undertaking a full-custom design. Cell-based ASICs also yielded a smaller die than did products using the then-dominant gate array architecture. Those improvements came directly from the highly flexible cell-based architecture, which eliminated almost all restrictions on how an ASIC can be created.
Silicon has continued to advance at the cadence set by Moore's Law, moving through 0.25-micron and finer geometries to reach today's 90-nanometer technology, bringing ever-greater levels of integration to cell-based ASIC products. But this high level of integration has become increasingly difficult to use, as well as time-consuming to implement and expensive to apply. These problems have grown to such magnitude that the very flexibility that made cell-based the preferred ASIC architecture has now put these products out of the reach of most users and infeasible for use in many systems.
Thus, the cell-based ASIC's strength has become a weakness for those companies that don't have large teams of engineers and even larger R&D budgets.
The increasing cost, time and risk to develop a semicustom chip is well documented and has served as a major impetus to the arrival of alternative solutions, including PLDs but especially off-the-shelf ASSPs.
PLDs on the rise
PLDs have benefited more than ASICs from advances in process technology over the past decade, opening up a host of new applications for programmable solutions.
While both PLDs and ASICs have delivered gains in speed, reductions in die size and decreases in power consumption with each generation, these improvements are more meaningful to the user in PLDs than in ASICs. For more and more systems that had been on the margin, PLDs now offer a technically feasible solution where ASICs had previously been the only option.
Because of this, PLDs no longer are exclusively tied to the networking-equipment market roller coaster and should enjoy continuing gains in the automotive, consumer and industrial areas. With PLDs leading the industry in the introduction of leading-edge silicon and with prices declining because of the shift to 300-mm wafer production, PLDs should be the fastest growing of the three core silicon solutions through the end of the decade, although they will generate the smallest amount of revenue.
ASIC makers have not been content to sit still and watch their market stagnate while ASSPs and PLDs flourish. These companies believe they have found a future in a new product: structured ASICs, the gate array of the new millennium.
These products, much like their gate array ancestors, offer designers the promise of faster turn times and lower up-front costs than cell-based ASICs although these advantages come at a higher unit price and with performance and power consumption penalties.
The concept of structured ASICs is sound, but iSuppli believes it will take several years before these products can make a meaningful revenue impact on the industry. As a result, iSuppli now forecasts the market will grow to the range of $250 million in 2007.
With only a limited number of structured-ASIC design wins to date approximately 70 in 2003 it would be extremely difficult for the market to grow much faster than that, although our analysis does have room for some upside potential. Vendors in the market, and suppliers to those vendors, need to be committed for the long haul if they want to profit from this business. Those companies that look to structured ASICs as a quick fix to shore up flat or declining cell-based ASIC revenues in the short term are almost certain to be disappointed.
The fact that iSuppli's forecast may seem low should not be interpreted as outright pessimism over the structured-ASIC's prospects. In fact, iSuppli is relatively optimistic about these devices' potential for success, but it will take more than three or four years before that success makes a meaningful contribution to the bottom line.
The designer's choice
Perhaps the most important criterion when making a core silicon choice is the nature of an end system's value. If a system derives much of its value from its features, and silicon can provide meaningful differentiation to the end product, then ASICs or PLDs have the edge over ASSPs, with the decision between the former two types of parts being made using criteria including total cost of ownership, power consumption and time-to-market.
However, end products that have become more commodity-like or that are standards-driven are ideal candidates for ASSPs. Thus, iSuppli believes that one of the electronics industry's most important trends is the general shift to this type of product.
PCs, of course, made the transition to commodity status many years ago, and explosively growing consumer products such as DVD players and now DVD recorders evolve very rapidly from custom to off-the-shelf silicon architectures. Even applications traditionally served by ASICs, such as cellular handsets, are moving at least in part to chip set approaches. This is happening as early adopters are supplemented by customers who are looking for nothing more than a basic system, where the core silicon socket is best filled with an ASSP.
In the future, innovative architectures such as hybrid FPGA/ASICs or FPGA/ASSPs will deliver the best of all worlds, combining programmability and flexibility only where needed, to minimize cost with a standard-product availability and pricing. Similarly, additional embedded processors could bring the same type of benefits to ASSPs as do FPGA blocks, with even better flexibility.
The ultimate embodiment of this philosophy could be a pure processor array, able to implement virtually any function. However, this is not yet an economically or, in many cases, technically feasible approach.
While these types of products have been discussed and researched for almost a decade, they remain on the horizon, not on the vendor's shelf. Although iSuppli expects continued innovation and fascinating product announcements, the revenue impact of these advanced architectures will not be felt before the end of the decade. Still, there could well be a major upturn in design wins three to five years from now.
Overall, iSuppli believes that the era of Makimoto's Wave has come to an end and that a new paradigm is now in place, one where industry growth is driven by standard silicon.
PLD and ASSP vendors will be the main beneficiaries of this new chip order and appear to have a solid future. ASICs, while continuing to enjoy a solid base, will lag far behind the overall semiconductor industry for the foreseeable future. As a result, iSuppli expects continuing consolidation of market share among the top-tier ASIC suppliers; second-tier and lower vendors will need to consider just how seriously they want to continue to pursue this business.
For system designers, the increasing competition and quickening pace of innovation among the three technologies will yield an increasingly rich array of core silicon options. Forearmed with knowledge about the varying advantages and disadvantages of each option, designers can take a lot of the guesswork and chance out of this high-stakes game of paper, rock, scissors.