LSI's RapidChip family aims to speed migration from FPGAs

Ronald Wilson

January 17, 2005

Ronald Wilson

MILPITAS, Calif. — LSI Logic Corp. announced Monday (Jan. 17) the next family in their expanding array of structured ASIC products, the Integrator-2.

Comprising eight new slices and reaching from 1.3 to 5.6 million useable logic gates, the family responds to needs voiced by early RapidChip customers and feedback from prospects still using cell-based design flows.

Yousef Khalilollahi, product marketing director for the RapidChip line, said customer and prospect feedback had clustered in three areas. First, there was an unending hunger for more memory, both in the size of large on-chip memory arrays and, in a number of instances, for smaller, distributed memory blocks.

Second, there was a need for very efficient controllers and interfaces to the latest external DRAM and SRAM devices.

And third, there was strong interest in expediting the migration process from FPGAs to RapidChip devices.

The need to expedite the migration was based on two phenomena, according to Khalilollahi. First, LSI is finding strong interest in RapidChip from design teams trying to consolidate multiple FPGAs into a single, low cost device. They are trying to do this without a complete redesign from the register-transfer (RTL) level on down. Second, many ASIC design teams are using FPGAs as prototyping vehicles for logic verification, and want to migrate the verification design directly to an ASIC, without having to maintain separate verification and product RTL code sets.

To meet these needs, LSI has made a number of structural changes to the Integrator RapidChip slice. The configurable I/O pad was upgraded to support DDR2, QDR2, RLDRAM2, FCRAM and other fast signalling standards, with impedance and slew control and integrated terminations. PHY hard macros have been inserted just inside the pad ring to support SPI4.2, SFI and source-synchronous 800 Mb LVDS. A firm macro for Denali's DDR controller has also been developed.

Another major change has been to the memory architecture, both to support large numbers of memory instances and to ease migration from memory-rich FPGAs. The devices now have both a large, highly-configurable dual-port matrix-RAM as well as the ability to form small RAM blocks from the logic fabric itself. The largest device can have up to 7.9 Mbits of RAM and up to 344 diffused RAM instances.

LSI is now accepting orders the Integrator-2 family.