PHYSICAL IC TOOLS: Three tout more nimble physical designSanta Cruz, Calif. Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference. New products include a fast design-rule checking (DRC) tool, a combined power and signal-integrity signoff solution, and a physical-synthesis suite that takes variability into account.
Magma Design Automation Inc. this week will release Quartz-DRC, which claims to verify any chip design in two hours or less. Apache Design Solutions Inc. is rolling out PsiWinder, a critical-path analysis tool that considers both power and crosstalk. And Sierra Design Automation Inc. will announce Pinnacle 2.0, which allows concurrent multimode and multicorner analyses of timing, area, power and signal integrity.
Because it promises a next-generation IC physical-verification solution, Quartz-DRC has been one of the most anticipated products in Magma's Cobra release. The product will attempt to challenge Mentor Graphics Corp.'s longstanding market lead in this sector with its Calibre DRC and LVS (layout vs. schematic) products.
Quartz-DRC technology was originally developed by Mojave Design, a 2002 startup that Magma acquired last year. "Most of the DRC and LVS tools in existence were all designed in the early to mid-1990s," said Mojave founder John Lee, now the general manager of Magma's physical-verification business unit. "That's a long time for EDA tools to be in the marketplace and be unchallenged."
Lee said Quartz-DRC has functionality equivalent to that of Mentor's Calibre or Synopsys' Hercules tools but that it provides that functionality in very different fashion: Quartz-DRC runs over distributed Linux networks in a way that's scalable over 50 or more CPUs.
LVS capability will be handled in a separate product, Quartz-LVS, slated for release later this year. Magma is working on design-for-manufacturability features for Quartz-DRC, but those aren't announced as yet. Extraction is handled separately by Magma's Quartz-RC product or by extraction products in third-party IC layout flows. Also missing is the wealth of foundry rule decks available for Mentor's Calibre. As of now, a TSMC 90-nanometer rule check is available for Quartz-DRC, and IBM has plans for 65-nm support, Lee said.
With its distributed processing capabilities, Quartz-DRC claims to run any design of any size within two hours provided you throw enough CPUs at it. In one benchmark example, a 200 million-transistor graphics processor with a 13-Gbyte GDSII file ran in 1.5 hours on a network of 50 workstations. Magma claimed that "tool X" took 44 hours in the same benchmark.
But if tool X was Calibre, Joe Sawicki, general manager of Mentor's design-to-silicon division, doesn't seem concerned.
"The only reports we have on Quartz-DRC and -LVS are secondhand from individuals who are not using Calibre's performance features and who are trying to pass off apples-to-oranges benchmarks as valid comparisons of tools," he said.
Lee said Magma has run experiments with Linux networks of more than 100 workstations, and he said the speed of the tool increases linearly as more are added. "Overhead is in the noise," he said. The product does not, however, offer multithreading for multi-CPU workstations.
Lee said Quartz-DRC has met foundry requirements for accuracy and that the tool is more accurate than existing solutions when it comes to modeling density and chemical-metal polishing effects. That's because it isn't restricted to "windows" of time and can calculate density at any point in a design, he said.
Input includes a GDSII layout file and a foundry rule deck. Although it's completely automatic, the product also has a Tcl interface that allows users to customize rule checks and output text reports, with the ability to cross-probe into Magma or third-party layout environments.
What makes Quartz-DRC so fast, Lee said, is fine-grained parallelism. "We can take a single DRC job and break it into thousands of smaller jobs, each scheduled on a Linux farm," he said. Also, the tool can process a number of commands simultaneously, on different CPUs.
Quartz-DRC is available now, although Magma has not announced pricing. Quartz-LVS is to follow later this summer.
Combining power, crosstalk
Well before chip designs reach the DRC stage, designers need to verify timing. Enter Apache's PsiWinder, a critical-path and clock tree analysis tool that considers crosstalk and dynamic-power integrity effects on chip timing. It's Apache's first solution to address crosstalk noise, said CEO Andrew Yang. "Because of the impact of noise on timing, it's important to combine power integrity and crosstalk noise analysis," he said.
PsiWinder provides a transient simulation of the dynamic Vdd/Vss noise waveforms that come out of the Apache RedHawk dynamic-power analyzer. To do this, it includes 10 licenses of Apache's NSpice product for distributed simulation over Linux or Unix workstations. PsiWinder's approach is unique, Yang said, because other solutions assume power supply noise is static inside timing windows, instead of taking "time point by time point" noise waveforms.
Other EDA solutions also separately analyze power integrity noise and crosstalk noise, Yang said. "These two sources of noise need to be concurrently handled, and ideally they should be handled at every time step because they are analog noise waveforms in nature," Yang said.
To use PsiWinder, designers must first identify critical paths for analysis. "With something as accurate as true Spice, you cannot traverse every single path in an SoC [system-on-chip] design," Yang noted. In one benchmark, he said, PsiWinder handled around 1,000 paths in an overnight run on 10 CPUs.
Inputs to PsiWinder include Vdd/Vss noise waveforms, a Spice netlist and library, the critical paths selected for analysis, and coupled parasitic information (including the full coupling effects). The user does not need to provide any test vectors, Yang said, and "there is no need to hack the Spice netlist."
PsiWinder then launches jobs on multiple machines and comes back with a timing report. Users can also back-annotate results to layout, since RedHawk has chip layout information. "We are working with quite a few customers who are seriously considering Spice signoff for clock networks and critical paths," said Yang.
PsiWinder, which requires RedHawk, will be available in the third quarter starting at $150,000.
Design for variability
At Sierra, the new mantra is "design for variability." That means the Pinnacle physical-synthesis tool can concurrently optimize timing, area, power and signal integrity across all operating modes and corners, rather than one corner at a time, as is the case with many existing tools. "We've come up with a way that you can do it all in one shot, rather than having that expensive iteration in the end," said Shankar Krishnamoorthy, Sierra's CTO.
New capabilities in Pinnacle 2.0 include an adaptive variability engine, a "signoff quality" timing analyzer and enhancements to the Detailed Native Analysis (DNA) kernel that underlies the physical-synthesis tool. The kernel now supports multiple operating modes and metal interconnect variations.
A cell phone chip, for example, might have several operating modes, including sleep, standby and active, each with its own timing frequency and constraints. It will also have different process, temperature and voltage corners and, because of on-chip metal variation, interconnect corners such as maxR (maximum resistance) and minC (minimum capacitance).
The timing engine in Pinnacle has added support for on-chip variation, multiple modes, multiple corners, multiple Vdd and complex clocking. While Sierra calls it "signoff quality," it's not meant to replace the widely used Synopsys PrimeTime product, Krishnamoorthy said. Rather, the intent is to bring this implementation timer closer to the level of quality found in final-signoff timers.
The adaptive variability engine accounts for variability at every stage of the design flow and optimizes all metrics concurrently, Krishnamoorthy said. Further, he noted, it allows variability analysis early in the physical-design flow. Users define variability "scenarios" consisting of various combinations of modes and corners. The DNA kernel then does a "one-shot optimization" over all of those scenarios, Krishnamoorthy said.
Sierra, he said, has gone up to 15 or 16 mode and corner combinations in one run. That's possible, he said, because all the scenarios are represented by one timing graph, which he called the "biggest innovation" in the Pinnacle 2.0 solution. Other tools, he maintained, would require a different graph for each scenario.
Pinnacle 2.0 is available now and has already had tapeouts, Sierra said. Prices begin at $395,000 for a one-year license.