Intel to discuss trigate transistors at VLSI Symposium
LONDON — Intel Corp. is scheduled to discuss tri-gate transistors at the upcoming VLSI Technology Symposium, which takes place in Honolulu, Hawaii, June 13 to 15.
According to the advanced program Intel researchers from Hillsboro, Oregon, have combined a fully depleted trigate transistor architecture with high-k gate dielectrics, metal-gate electrodes and strain engineering.
As far as we know Intel has not, so far, disclosed the high-k gate dielectric and metal gate electrode regime it is using for any advanced CMOS processing. Despite the fact that there are whole sessions on high-k and metal-gate stack integration at the conference Intel is not due to present in these sessions.
It remains to be seen whether Intel will disclose details of its high-k metal-gate regime in its trigate paper, or indeed the gate dimensions and intended manufacturing process node. Neither is mentioned in the abstract contained in the advanced program.
Without mentioning materials or dimensions in the asbstract the Intel researchers claimed that high performance NMOS and PMOS trigate transistors have been demonstrated. They also said that contributions of strain, substrate orientation, high-k dielectrics in the plural and low channel doping are investigated for multiple channel dimensions and fin profiles.
The Intel paper is due to presented at 3:25pm local time in Hawaii on Tuesday, June 13.
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