Japan's TEL selected for European 'gate-stack' project
GRENOBLE, France — Chip quipment vendor Tokyo Electron Ltd. has signed an agreement with France's CEA LETI (Laboratory of Electronics and Information Technologies) to develop a CMOS gate stack that includes a high-k insulator and metal gate materials and deposition steps for 45-nm and lower manufacturing process nodes.
The partnership is based at CEA Leti's facility, here, for processing 300-mm diameter wafers known as Nanotec300 and opened April 22.
Nanotec300 has already signed several collaborative contracts, including a four-year contract with the three partners of the Crolles Alliance — Freescale Semiconductor, Philips and STMicroelectronics.
Under the terms of the deal, TEL is to provide its "Telformula" batch thermal processing system and its single-wafer "Trias" system. In addition to the basic development of high-k and metal gate materials, the joint development program will also address pre- and post-deposition processes. "We expect to advance quickly to an integrated customer solution for advanced high-k, metal gate stack," said Peter Horii, vice president for the operations and sales business unit of Tokyo Electron Europe Limited, in a statement.
"Thanks to this collaboration, CEA Leti will be in position to propose new 300-mm cutting edge module integration technology to its collaborative partners," Olivier Demolliens, Nanotec300 manager at CEA Leti, said in the same statement.
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