EEMBC Unveils Plans for Multicore Benchmarks

Bernard Cole

February 20, 2007

Bernard Cole

El Dorado Hills, Ca. - The Embedded Microprocessor Benchmark Consortium today announced plans to soon roll out new benchmarks that will address multiprocessing systems, multicore processors, and multithreaded processors.

The EEMBC effort, which has been underway since mid-2006, is being led by John Goodacre of ARM, who serves as chair of EEMBC's multiprocessing workgroup.

With the proliferation of multicore processor implementations," said Shay Gal-On, director of software engineering at EEMBC, "the need is growing for performance benchmarks that can give an accurate indication of the value of transitioning from a single core to a multicore system, in addition to determining the impact of system-level bottlenecks, such as those encountered when moving data on and off a multicore chip.

He said the soon to be released multicore benchmark suites will provide a standardized way to evaluate the benefits of concurrency while providing the scalability needed to support any number of multiple cores.

The multicore benchmark software will initially support symmetrical multicore processors with shared memory and will utilize a thread-based API to establish a common programming model.

Targeted will be three forms of concurrency: task decomposition, multiple data stream processing, and the processing of multiple workloads. Task decomposition allows multiple threads to cooperate on achieving a unified goal and demonstrates a processor's support for fine grain parallelism.

Processing of multiple data streams uses common code running over multiple threads and demonstrates how well a solution can scale over scalable data inputs. Finally, multiple workload processing shows the scalability of a solution for general-purpose processing and activates concurrency over both code and data.

To implement this strategy on the benchmark level, said Gal-On, a test harness is being developed that will communicate with the benchmark through an abstraction layer that is analogous to an algorithm wrapper. This test harness will provide a flexible interface to allow a wide variety of thread-enabled workloads to be tested.

In addition to using some of the existing EEMBC benchmarks in its multicore-enabled benchmark suites, EEMBC has begun work on multicore-capable VOIP and H.264 benchmarks.