Enea debuts multicore OS combining AMP, SMP kernel supportESC Boston, Ma. - Enea has just announced availability of its OSE Multicore Edition, a unique and innovative kernel design that combines the advantages of both traditional Asymmetric Multiprocessing (AMP) and Symmetric Multiprocessing (SMP) while avoiding the disadvantages inherent in both programming models.
According to Mathis Bth, senior vice president of marketing at Enea, the new RTOS, redesigned from the ground up to support multicore designs, will help developers of advanced systems achieve the performance, scalability and ease-of-use needed to meet increasingly stringent market requirements.
He said it retains many of the advantages of SMP when it comes to simplicity, flexibility, application transparency and debugging. But it behaves like an AMP RTOS when it comes to scalability, determinism and performance.
OSE Multicore Edition provides a homogeneous and portable application framework with linear scalability for high speed processing applications while at the same time being a feature rich RTOS offering POSIX file systems, SMP threading and full IP networking support. API compatibility with Enea OSE means legacy OSE applications will be fully supported - guaranteeing a smooth transition to multicore processors.
In addition, said Bth, OSE Multicore Edition offers the option of a "friction free" execution model on individual processor cores that can host run-to-completion software at bare metal speed.
"Enea OSE Multicore Edition was primarily designed to meet the performance and scalability requirements in the networking market, but will address high performance applications equally well in a wide range of industry segments," he said.
The hybrid AMP/SMP kernel in OSE Multicore Edition is based on a number of distinct innovations:
* Essential services in OSE are implemented according to a micro kernel model which allows IP stacks, file systems, application loaders, etc. to be located on different cores, while applications can access these services regardless of location in the system (location transparency).
* A kernel that instantiates a separate scheduler on each core with associated data structures to preserve determinism and realtime characteristics.
* User defined process migration and load balancing based on low intrusion mechanisms to measure CPU load on each core.
* A lightweight kernel internal IPC mechanism called kernel events used to perform asynchronous, cross core transactions in order to avoid the use of fine-granular locking designs, which has a detrimental effect on performance.
To learn more, go to www.enea.com.